浅井 哲也

News and Updates

2016/ 07/23Naive Bayes classifier for dynamic branch prediction (APCCAS 2016)
2016/ 07/07A hardware cellular-automaton architecture for spatial pattern generation (NOLTA 2016)
2016/ 06/21Error tolerance analysis of deep learning hardware towards low-power memory implementation (IEEE TCAS2)
2016/ 06/08Image sensor/processor 3D stacked system featuring ThruChip interfaces (ESSCIRC 2016)
2016/ 05/09Reliability of error-injected hardware DBN (NOLTA Journal)
2016/ 05/06FPGA-based stream processing for frequent itemset mining (J. Circuits and Systems)
2016/ 04/21FPGA implementation of restricted Boltzmann machines (J. Circuits and Systems)
2016/ 04/053D stacked imager featuring ThruChip Interfaces (ITE Trans. MTA)
2016/ 03/31Hardware-Oriented Celullar Automata for Gaze Estimation (IEICE NOLTA Society Symposium)
2016/ 03/31Hardware Architecture for Online Frequent Items Mining (COOL Chips XIX)
2016/ 03/31Presentations at IEICE LSI and Systems Workshop 2016
2016/ 03/11Stream Processing Architectures for Frequent Itemset Mining (IEICE Reconfigurable Systems Workshop)
2016/ 03/10Deep Learning (CNN/RNN) Architectures (IEICE Reconfigurable Systems Workshop)
2016/ 01/13Memory-Error Tolerance of Hardware Deep Belief Networks (ISCAS 2016)
2015/ 12/14Stochastic Resonance induced by Internal Noise (NOLTA Journal)
2015/ 12/05Whereabouts of Neuromorphic Engineering and Machine-learning Hardware (Invited Paper, JNNS)
2015/ 10/29Overview of Machine Learning Hardware (Invited, NICT-CiNet Seminar)
2015/ 09/01Nonlinear Image Processing Algorithms (NICT-CiNet Seminar)
2015/ 08/16Overview of Neuromorphic Systems / Chips (STARC Advanced Seminar; Neuro Chip 1)
2015/ 08/01Nonlinear / Noise-driven Information Processing (NOLTA 2015)
2015/ 04/07Neural Networks on FPGA (Invited Talk at JNNS Symposium 2015)
2015/ 04/02Won the Best Paper Award! (Research Institute of Signal Processing Japan)
2015/ 03/31Digitral Machine Learning Systems (Invited Talk at Brainware Engineering Workshop)
2015/ 03/11Image sensor/digital logic 3D stacked module (2015 VLSI Symposia)
2015/ 03/05TCI crosstalk rejection based on blind source separation (IEEE TCAS-II)
2015/ 01/13A scalable FPGA-based architecture for locality-sensitive hashing (IEICE Conference)
2015/ 01/05Nonlinear Signal-Processing Gadgets (NCSP 2015)
2014/ 12/29An accelerator for frequent Itemset mining from data stream (SASIMI 2015)
2014/ 12/25FPGA implementation of hardware-oriented RDCA (NOLTA Journal)
2014/ 12/09Caching memcached at reconfigurable network interface (IPSJ Journal)
2014/ 10/28Won the Best Student Paper Award at JKCCS 2014
2014/ 10/15Presentation at IEICE ICD/CPSY Workshop
2014/ 10/02Achieving higher performance of memcached by caching at network interface (ICFPT 2014)
2014/ 09/06Hardware architecture for accelerating key-value retrieval implemented on FPGA (JKCCS 2014)
2014/ 09/03Low-power NV microcontrollers with transparent on-chip instruction cache (CS Journal)
2014/ 08/31Transparent on-chip instruction cache for NV microcontrollers (CENICS 2014)
2014/ 08/20Mainly-static/partially-dynamic reconfigurable array accelerator (A-SSCC 2014)
2014/ 07/15Self-driven Stochastic Resonance (IEICE NetSci/CCS workshop 2014).
2014/ 07/10Low-power asynchronous digital pipeline based on stochastic ogic gates (ELEX)
2014/ 06/18Hardware-Oriented Reaction-Diffusion Steganography (NOLTA Journal)
2014/ 06/18Low-Power Logic Gates utilizing Stochastic Resonance (NOLTA Journal)
2014/ 06/09Won the Student Presentation Award of 2013 IEICE CS Workshop!
2014/ 06/06Stochastic Resonance Applications (NOLTA 2014, Special Session)
2014/ 06/04Caching memcached at reconfigurable network interface (FPL 2014)
2014/ 05/09Morphic Architectures for Molecular Architectonics (MOLARCH WS)
2014/ 05/01Machine Learning of Motion Vectors exploiting High-Speed Imaging (JSP)
2014/ 04/08Presentation at LSI and Systems Workshop 2014
2014/ 03/03Won the student paper award (NCSP 2014)
2014/ 02/21Stochastic Circuit Design for Molecular Architectonics (MolArch Workshop 2014)
2014/ 01/08Dynamic Load Generator for Memcached Evaluation (IEICE)
2014/ 01/07FPGA implementation of a novel stereo vision algorithm (CSC 2014)
2014/ 01/06Machine Learning of Motion Vectors exploiting High-Speed Imaging (NCSP 2014)
2013/ 12/17Low-power flash-based microcontrollers architecture (ARC workshop)
2013/ 12/11Stereo Matching VLSI Architectures (STARC Symposium 2014)
2013/ 11/20FPGA Implementation of Cached NIC for Memcashed (IEICE RECONF Workshop)
2013/ 11/19Machine learning of motion vectors on FPGA (IEICE ICD Workshop)
2013/ 11/18Won the best student paper award of NOLTA 2013!
2013/ 11/13Journal Paper: C-based design for dynamically reconfigurable hardware
2013/ 10/18FPGA Implementation of Reaction-Diffusion Cellular Automata (SRBA 2013)
2013/ 10/15Hardware-oriented stereo vision algorithm and its FPGA implementation (ICECS 2013)
2013/ 09/27A restricted dynamically reconfigurable architecture (ReConFig 2013)
2013/ 09/27Image steganography based on RD models and its FPGA implementation (SICE SSI 2013)
2013/ 09/07Low power reconf and stream processors (IEICE Reconf WS)
2013/ 08/08Presentation: Depth map FPGA (VDEC Designer's Forum)
2013/ 08/06Presentation: dynamically reconfigurable technologies (SASIMI 2013)
2013/ 07/22Journal Paper: chaotic Resonance (J. Signal Processing)
2013/ 07/12Presentation: logical stohastic resonance (IEICE NetSci/CCS workshop, 2013)
2013/ 05/27Presentation: image steganography processor (NDES 2013)
2013/ 05/16Presentation: reaction diffusion steganography (IEICE CCS WS, 2013)
2013/ 05/16Presentation: applications of nonlinear systems (NOLTA 2013)
2013/ 05/15Award: student poster award at LSI and Systems Workshop 2013!
2013/ 04/23Presentation: asynchronous digital circuits based on stochastic resonance (NANOENERGY 2013)
2013/ 04/22Jounal Paper: single-image super resolution on FPGA (J. Signal Processing)
2013/ 04/17Presentation: C-based design for dynamially reconfigurable hardware (IEICE IN 2013)
2013/ 04/17Presentation: implementing window-join on DRP HPCS 2013
2013/ 03/27Presentation: restricted dynamically reconficurable processor (SACSIS 2013)
2013/ 03/11Award: Student Paper Award (NSCP'13)
2013/ 01/03Presentation: sensor-processor 3D integration (STARC Symposium 2013)
2013/ 01/03Presentation: FPGA implementation of single-image super resolution (NCSP 2013)
2012/ 12/11Presentation: Stream processing on dynamically reconfigurable hardware (ARC 2013)
2012/ 12/04Presentation: Array-enhanced chaoric resonance (IEICE NLP, Jan. 2013)
2012/ 09/24Journal Paper: Noise-driven active transmission line (J. Signal Processing)
2012/ 07/23Presentation: Nonlinear Analog Gadgets (AsiaNANO 2012)
2012/ 07/02Presentation: Reaction-diffusion media with memristors (CNNA 2012)
2012/ 06/18Presentation: Noise-induced spike transmission on electrical axon (NOLTA 2012)
2012/ 05/22Journal Paper: Nonlinear Electric Circuits (J. Signal Processing)
2012/ 05/02Presentation: low power processors (LSI and Systems Workshop 2012)
2012/ 04/02Presentation: Stochastic resonance in myelinated axons (ICCNS 2012)
2012/ 03/09Award: Student Paper Awards (NSCP'12)
2012/ 01/13Presentation: 2012 IEICE General Conference
2012/ 01/13Presentation: Nonlinear and neuromorphic electrical circuits (NCSP 2012)
2011/ 09/15Presentation: Noise-induced phase synchronization among analog MOS oscillator circuits (FNL)
2011/ 07/07Presentation: 2011 IEICE Society Conference (Sapporo, Japan)
2011/ 06/20Journal Paper: SR system consisting of single OTA (NOLTA Journal)
2011/ 06/10Presentation: IEICE NLP workshop (Hokkaido, 30th Jun, 2011)

Towards Emerging System/Circuit/Device Co-Design Science and Technologies

Tetsuya Asai

Professor (LINAS), IST, Hokkaido University (Visiting Fellow, University of the West of England)
Office: IST, M-BLDG, 2F, Room M206 (TEL: +81 11-706-6080, FAX: +81 11-706-7890)
E-mail: asai at ist.hokudai.ac.jp

Research Topics

My research interests concentrate on integrated nano-systems exploiting innovative circuit/device co-design science and technologies, to develop "device-aware" circuits and systems that naturally utilize essential properties of emerging nano materials and devices, through interdisciplinary technologies and studies on semiconductor physics, integrated circuit engineering, information science, nonlinear theory and its applications, neural science, etc. For example, I am handling1) emerging research architectures for nano CMOS, single electron/molecule devices, emerging memory devices (memristors), etc., 2) emerging circuit/device co-design architectures for deep learning, neuromorphic computing, nonlinear analog computing, beyond Neumann computing, 3) functional imaging and novel image processing as well as its integrated circuit systems, and so on.

Academic Societies

  1. Institute of Electrical and Electronic Engineers (IEEE)
  2. The Institute of Electronics, Information and Communication Engineers (IEICE)
  3. Japan Society of Applied Physics (JSAP)
  4. Japanese Neural Network Society (JNNS)
  5. Research Institute of Signal Processing (RISP)

Lectures

  1. Advanced Integrated Circuits and Systems (undergraduate school)
  2. Electrical and Electronic Engineering Laboratories (undergraduate school)
  3. System Applications of VLSIs (graduate school)
  4. Integrated Information Processing (graduate school)

Doctoral Thesis

  • Analog Integrated Circuits for Motion Detection and Visual Tracking Circuits based on Biological Vision Systems
    (edited by SIPEC / original)