IST, Hokkaido University, Japan

News and Updates

Presentation at 2012 IEICE General Conference

安達 琢, 平尾 岳志, 浅井 哲也, 本村 真人, "低消費電力プロセッサのための連鎖型データパスの提案I," 電子情報通信学会総合大会, (岡山), 2012年3月.
平尾 岳志, 安達 琢, 浅井 哲也, 本村 真人, "低消費電力プロセッサのための連鎖型データパスの提案II," 電子情報通信学会総合大会, (岡山), 2012年3月.
石村 憲意, 浅井 哲也, 本村 真人, "外力を受けるチュア発振回路におけるカオス共鳴," 電子情報通信学会総合大会, (岡山), 2012年3月.
宮 曦媛, 浅井 哲也, 本村 真人, "パルス演算に基づくLDPCエラー訂正処理とそのアーキテクチャ," 電子情報通信学会総合大会, (岡山), 2012年3月.
松浦 正和, 浅井 哲也, 本村 真人, "ディジタル発振器群における雑音誘起位相同期," 電子情報通信学会総合大会, (岡山), 2012年3月.
尹 征一, 真田 祐樹, 浅井 哲也, 本村 真人, 竹中 崇, "ウェーブレット縮退の多段化によるデノイズ画像処理とそのLSIアーキテクチャ: Part I," 電子情報通信学会総合大会, (岡山), 2012年3月.
真田 祐樹, 尹 征一, 浅井 哲也, 本村 真人, 竹中 崇, "ウェーブレット縮退の多段化によるデノイズ画像処理とそのLSIアーキテクチャ: Part II," 電子情報通信学会総合大会, (岡山), 2012年3月.
[details]Fri, 13 Jan 2012 17:54:22 +0900

Nonlinear and neuromorphic electrical circuits (NCSP 2012)
Gonzalez-Carabarin L., Asai T., and Motomura M., "Noise-assisted spike transmission on an array of electrical FitzHugh-Nagumo models," 2012 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA (Mar. 4-6, 2012).
Adachi T., Asai T., and Motomura M., "A memristor-based synaptic device having an asymmetric STDP time window," 2012 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA (Mar. 4-6, 2012).
Ishimura K., Asai T., and Motomura M., "Chaotic resonance in forced Chua’s oscillator," 2012 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA (Mar. 4-6, 2012).
Gong X., Asai T., and Motomura M., "Excitable reaction-diffusion media with memristors," 2012 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA (Mar. 4-6, 2012).
Matsuura M., Asai T., and Motomura M., "Noise-induced phase synchronization in digital counters," 2012 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA (Mar. 4-6, 2012).
[details]Fri, 13 Jan 2012 17:53:21 +0900

Noise-induced phase synchronization among analog MOS oscillator circuits (FNL)
Utagawa A., Asai T., and Amemiya Y., "Noise-induced phase synchronization among analog MOS oscillator circuits," Fluctuation and Noise Letters, in press.
[details]Thu, 15 Sep 2011 17:38:06 +0900

Presentation at 2011 IEICE Society Conference (Sapporo, Japan)
吉田 和徳, 宇田川 玲, 浅井 哲也, 本村 真人, "正帰還アンプのヒステリシスを利用した極低電圧・低消費電力 メモリ回路の試作と評価," 電子情報通信学会ソサイエティ大会, (札幌), 2011年9月.
安達 琢, 浅井 哲也, 本村 真人, "抵抗変化型メモリを用いたアナログ STDP シナプスデバイス," 電子情報通信学会ソサイエティ大会, (札幌), 2011年9月.
石村 憲意, 浅井 哲也, 本村 真人, "Chuaのダブルスクロール系におけるカオス共鳴," 電子情報通信学会ソサイエティ大会, (札幌), 2011年9月.
宮 曦媛, 浅井 哲也, 本村 真人, "メモリスタを拡散結合に用いた興奮場モデルの数値解析," 電子情報通信学会ソサイエティ大会, (札幌), 2011年9月.
松浦 正和, 浅井 哲也, 本村 真人, "雑音誘起位相同期の応用に向けた水晶発振器の位相変調回路," 電子情報通信学会ソサイエティ大会, (札幌), 2011年9月.
高萩 和宏, 松下 拓道, 雨宮 好仁, 佐野 栄一, "ウェイクアップ受信器のための低消費電力検波器・高利得増幅器," 電子情報通信学会ソサイエティ大会, (札幌), 2011年9月.
久保 圭史, 池辺 将之, 雨宮 好仁, 佐野 栄一, "スタック構造による低電力CMOS論理回路," 電子情報通信学会ソサイエティ大会, (札幌), 2011年9月.
[details]Thu, 7 Jul 2011 10:47:17 +0900

SR system consisting of single OTA (NOLTA Journal)
Utagawa A., Asai T., and Amemiya Y., "Stochastic resonance in simple analog circuits with a single operational amplifier having a double-well potential," Nonlinear Theory and Its Applications, in press.
[details]Mon, 20 Jun 2011 18:42:57 +0900

Oral presentations at IEICE NLP workshop (Hokkaido, 30th Jun, 2011)
安達 琢, 赤穂 伸雄, 浅井 哲也, 本村 真人, "メモリスタ-CMOSハイブリッド回路による非対称STDPシナプスデバイス," 電子情報通信学会非線形問題研究会, (北海道), 2011年6月.
石村 憲意, 浅井 哲也, 本村 真人, "ダフィング方程式に基づく電子回路向けカオスダイナミクスと アナログ電子回路によるカオス共鳴実験," 電子情報通信学会非線形問題研究会, (北海道), 2011年6月.
宮 曦媛, 赤穂 伸雄, 浅井 哲也, 本村 真人, "ユニポーラ型ReRAMネットワークを用いた経路探索アナログガジェット," 電子情報通信学会非線形問題研究会, (北海道), 2011年6月.
松浦 正和, 宇田川 玲, 浅井 哲也, 本村 真人, "微小電流による位相変調が可能なアナログCMOS発振器群における雑音誘起位相同期," 電子情報通信学会非線形問題研究会, (北海道), 2011年6月.
[details]Fri, 10 Jun 2011 16:27:02 +0900

Professor Motomura received the IEICE Achievement Award
受賞日　2011年　5月28日
授与団体　電子情報通信学会
賞名　　　第47回（平成22年度）業績賞
受賞内容　「動的再構成プロセッサの研究開発とその画像処理機器応用」
受賞者　　本村真人、粟島亨、藤井太郎（ルネサスエレクトロニクス）

同賞は、電子工学および情報通信に関する発明・理論・実験・手法などの基礎研究の促進、また新しい機器や方式の開発など明確な業績があると評価された研究に授与されるもので、1963年に設立されました。本受賞は、昨年度まで本村教授が日本電気株式会社において長年にわたりリードしてきた動的再構成プロセッサの研究開発が、その新規性と産業応用の両面で、世界をリードする業績であると認められたことによるものです。本村教授は、当研究室においても、同分野をさらに発展させる研究活動を引き続き行っていく予定です。
[details]Sat, 28 May 2011 11:05:00 +0900

Professor Masato Motomura joined with us, welcome!!
[details]Fri, 1 Apr 2011 10:37:00 +0900

IEEE CIS Japan, 2010 Young Researcher Award
赤穂 伸雄, 浅井 哲也, 柳田 剛, 川合 知二, 雨宮 好仁, "バイポーラ型抵抗変化メモリ素子を用いたSTDPシナプスデバイス," IEEE CIS Japan 2010年度Young Researcher Award（IEICE NC研究会）, Mar. 2011.
[details]Mon, 28 Feb 2011 15:29:30 +0900

A Neuromorphic MOS Circuit of Eigenmannia (NOLTA Journal)
Fujita D., Asai T., and Amemiya Y., "A Neuromorphic MOS Circuit imitating Jamming Avoidance Response of Eigenmannia," Nonlinear Theory and Its Applications, vol. 2, no. 3, (2011), in press.
[details]Tue, 11 Jan 2011 12:58:21 +0900

High-fidelity pulse density modulation in neuromorphic electric circuits (NOLTA Journal)
Utagawa A., Asai T., and Amemiya Y., "High-fidelity pulse density modulation in neuromorphic electric circuits utilizing natural heterogeneity," Nonlinear Theory and Its Applications, vol. 2, no. 3, (2011), in press.
[details]Tue, 11 Jan 2011 12:55:10 +0900

Analog CMOS gadgets (IEICE public conference 2011)
吉田 和徳, 宇田川 玲, 浅井 哲也, 雨宮 好仁, "サブスレッショルド領域で動作するロジックメモリ回路の低電圧化の検討," 電子情報通信学会総合大会, (東京), 2011年3月.
安達 琢, 赤穂 伸雄, 浅井 哲也, 雨宮 好仁, "非対称の時間窓を持つメモリスタSTDPシナプスデバイス," 電子情報通信学会総合大会, (東京), 2011年3月.
宮 曦媛, 赤穂 伸雄, 浅井 哲也, 雨宮 好仁, "ユニポーラ抵抗変化メモリのアナログ応用〜迷路の経路探索〜," 電子情報通信学会総合大会, (東京), 2011年3月.
松浦 正和, 宇田川 玲, 浅井 哲也, 雨宮 好仁, "電流ノイズに鋭敏なCMOS発振器群における雑音誘起位相同期," 電子情報通信学会総合大会, (東京), 2011年3月.
石村 憲意, 宇田川 玲, 浅井 哲也, 雨宮 好仁, "擬似ダフィン系のアナログ電子回路におけるカオス共鳴," 電子情報通信学会総合大会, (東京), 2011年3月.
久保 圭史, 雨宮 好仁, 佐野 栄一, "カスコード構造による低電力CMOS論理回路," 電子情報通信学会総合大会, (東京), 2011年3月.
[details]Thu, 6 Jan 2011 18:06:09 +0900

ReRAM-based STDP synaptic device (IEICE NC, Oct, 2010)
赤穂 伸雄, 浅井 哲也, 柳田 剛, 川合 知二, 雨宮 好仁, "バイポーラ型抵抗変化メモリ素子を用いたSTDPシナプスデバイス," 電子情報通信学会 ニューロコンピューティング研究会, (北九州), 2010年10月.
[details]Fri, 1 Oct 2010 10:50:33 +0900

A HSPICE model of unipolar resistive RAMs (IEICE ELEX)
Akou N., Asai T., Yanagida T., Kawai T., and Amemiya Y., "A behavioral model of unipolar resistive RAMs and its application to HSPICE integration," IEICE Electronics Express, vol. 7, (2010), in press.
[details]Mon, 13 Sep 2010 10:56:00 +0900

ReRAM-based STDP synaptic devices (Nanoelectronics Days 2010)
Akou N., Asai T., Yanagida T., Kawai T., and Amemiya Y., "A ReRAM-based analog synaptic device having spike-timing-dependent plasticity," Nanoelectronics Days 2010, Aachen, Germany (Oct. 4-7, 2010).
[details]Mon, 13 Sep 2010 10:53:41 +0900

Array-enhanced stochastic resonance in neuromorhic circuits (ICONIP 2010)
Tovar G., Asai T., and Amemiya Y., "Array-enhanced stochastic resonance in a network of noisy neuromorhic circuits," The 1t7th International Conference on Neural Information Processing, Sydney, Australia (Nov. 22-25, 2010).
[details]Mon, 13 Sep 2010 10:50:51 +0900

On-chip power supply for subthreshold LSIs (ICOSSSE 2010)
Shimada H., Ueno K., Asai T., and Amemiya Y., "On-chip power supply for subthreshold-operated CMOS LSIs," The 9th International Conference on System Science and Simulation in Engineering, Iwate, Japan (Oct. 4-6, 2010).
[details]Thu, 26 Aug 2010 16:20:16 +0900

Low-voltage power supply regulator for subthreshold digital LSIs (SSDM 2010)
Ueno K., Shimada H., Asai T., and Amemiya Y., "Low-voltage power supply regulator for subthreshold-operated CMOS digital LSIs," 2010 International Conference on Solid State Devices and Materials, Tokyo, Japan (Sep. 22-24, 2010).
[details]Sat, 14 Aug 2010 21:16:41 +0900

Prof. Amemiya received the grade of Fellow from IEICE Electronics Society
雨宮 好仁, "量子集積デバイスに適した回路アーキテクチャの開拓に対する貢献," 電子情報通信学会エレクトロニクスソサイエティ平成22年度フェロー（フェロー称号贈呈式：2010年9月IEICEソサイエティ大会）
[details]Wed, 28 Jul 2010 14:16:47 +0900

Subthreshold CMOS gadgets (IEICE, Sep., 2010)
赤穂 伸雄, 浅井 哲也, 雨宮 好仁, "スパイクタイミングに依存してコンダクタンスが変化するメモリスタ神経デバイス," 電子情報通信学会ソサイエティ大会, (大阪), 2010年9月.
嶋田 英人, 上野 憲一, 浅井 哲也, 雨宮 好仁, "サブスレッショルドCMOS-LSIのためのオンチップ電源回路," 電子情報通信学会ソサイエティ大会, (大阪), 2010年9月.
松下 拓道, 佐野 栄一, 雨宮 好仁, "低電力ウェイクアップ受信機のためのPWM復調回路," 電子情報通信学会ソサイエティ大会, (大阪), 2010年9月.
吉田 和徳, 宇田川 玲, 浅井 哲也, 浅井 哲也, 雨宮 好仁, "サブスレッショルド SRAM セルの検討---完全サブスレッショルド型とテイル電流制限型の比較---," 電子情報通信学会ソサイエティ大会, (大阪), 2010年9月.
[details]Thu, 8 Jul 2010 10:19:04 +0900

HSPICE macromodel of unipilar ReRAMs (WOE 17)
Akou N., Asai T., Amemiya Y., Yanagida T., and Kawai T, "A behavioral model of unipolar resistive RAMs and its application to HSPICE integration," The 17th International Workshop on Oxide Electronics, Hyogo, Japan (Sep. 19-22, 2010).
[details]Thu, 1 Jul 2010 11:16:26 +0900

Noise-driven neuromorphic analog CMOS circuits (Neuro 2010)
Tovar G.M., Asai T., and Amemiya Y., "Neuromorphic CMOS analog circuit exhibiting array-enhanced stochastic resonance behavior with population heterogeneity," Neuro 2010, (神戸), 2010年9月.
[details]Thu, 1 Jul 2010 11:16:26 +0900

Invited Talk on Reaction-Diffucion Computers at CSD 2010 (UC 2010)
Asai T., "Reaction-diffusion computers on semiconductors --- A legacy from past adventures," The 1st International Workshop on Computing with Spatio-Temporal Dynamics (The 9th Internal Conference on Unconventional Computation), Tokyo, Japan (Jun. 21-25).
[details]Mon, 21 Jun 2010 10:01:27 +0900

Invited talk on noise-driven systems (The 15th Biotronics Workhop)
宇田川 玲, "次世代ナノエレクトロニクスに向けたゆらぎの役割と応用〜双安定系を例にとって〜," 第15回情報バイオトロニクス研究会, Sapporo, Japan (Jun. 11, 2010).
[details]Tue, 1 Jun 2010 09:54:00 +0900

Stochastic resonance in a simple CMOS circuit (NOLTA 2010)
Utagawa A., Asai T., and Amemiya Y., "Stochastic resonance in a simple electric circuit having a double-well potential ---Circuit experiments with a single operational amplifier---," 2010 International Symposium on Nonlinear Theory and its Applications, Krakow, Poland (Sep. 5-8, 2010).
[details]Mon, 31 May 2010 14:21:43 +0900

Sub-threshold current-reference circuit (Journal Paper)
Ueno K., Hirose T., Asai T., and Amemiya Y., "A 1-uW, 600-ppm/°C current reference circuit consisting of sub-threshold CMOS circuits," IEEE Transactions on Circuits and Systems II, (2010), in press.
[details]Mon, 31 May 2010 14:19:11 +0900

ICD Student/Young Researcher Poster Award
山本 和輝, 上野 憲一, 浅井 哲也, 雨宮 好仁, "サブスレッショルドCMOS LSIのためのナノワットDA変換器," 電子情報通信学会集積回路研究会 12月度学生・若手研究会 優秀若手研究ポスター賞, Mar. 2010.
[details]Tue, 23 Mar 2010 13:00:17 +0900

Neuromophic single-electron devices (Book Chapter)
Kikombo A.K., "Neuromophic LSI Architectures consisting of single-electron devices -- Edge detection and extraction with single-electron circuits --," Vision Sensors and Edge Detection, Sciyo (2010), in press.
[details]Tue, 23 Mar 2010 12:59:16 +0900

Neuromorphic CMOS integrated devices (ICCNS 2010)
Utagawa A., Asai T., and Amemiya Y., "Stochastic resonance in neuromorphic semiconductor devices having a double-well potential," The 14th International Conference on Cognitive and Neural Systems, Boston, USA (May. 19-22, 2010).
Tovar G., Asai T., and Amemiya Y., "Coupling-enhanced stochastic resonance in noisy neuromorphic devices," The 14th International Conference on Cognitive and Neural Systems, Boston, USA (May. 19-22, 2010).
Akou N., Asai T., and Amemiya Y., "Towards memristor-CMOS-hybrid semiconductor devices for neural networks," The 14th International Conference on Cognitive and Neural Systems, Boston, USA (May. 19-22, 2010).
[details]Tue, 23 Mar 2010 12:56:41 +0900

A subthreshold temperature sensor (Journal Paper)
Ueno K., Asai T., and Amemiya Y., "Low-power temperature-to-frequency converter consisting of sub-threshold CMOS circuits for integrated smart temperature sensors," Sensors and Actuators A: Physical, (2010), in press.
[details]Tue, 16 Mar 2010 14:07:42 +0900

A subthreshold CMOS resistor (Journal Paper)
Asai S., Ueno K., Asai T., and Amemiya Y., "High-resistance resistor consisting of a subthreshold CMOS differential pair," IEICE Transactions on Fundamentals of Electronics, Communications and Computer, vol. E93-A, (2010), in press.
[details]Tue, 2 Mar 2010 16:47:41 +0900

Stochastic Resonance in Electrical Circuits having a Double-Well Potential (IEICE NLP)
宇田川 玲, 浅井 哲也, 吉田 和徳, 雨宮 好仁, "電子回路で容易に実装可能な二重井戸ポテンシャル系における確率共鳴〜オペアンプ一個でできる確率共鳴実験〜," 電子情報通信学会 非線形問題研究会, (東京), 2010年3月.
[details]Tue, 16 Feb 2010 17:23:21 +0900

Subthreshold CMOS gadgets (IEICE, Mar., 2010)
上野 憲一, "MOSFETのSub-VTH動作を用いた低消費電力CMOS回路技術," 電子情報通信学会総合大会シンポジウム講演（サブスレッショルドCMOS回路技術）, (仙台), 2010年3月.
赤穂 伸雄, 浅井 哲也, 雨宮 好仁, "抵抗変化型メモリをシナプスに用いたニューラルネットワークにおける教師有り学習回路," 電子情報通信学会総合大会, (仙台), 2010年3月.
松下 拓道, 上野 憲一, 浅井 哲也, 雨宮 好仁, "LSIを間欠動作させるための低電力タイマースイッチ回路," 電子情報通信学会総合大会, (仙台), 2010年3月.
山本 和輝, 上野 憲一, 浅井 哲也, 雨宮 好仁, "時間軸上のパルス加算による低電力DA変換器," 電子情報通信学会総合大会, (仙台), 2010年3月.
吉田 和徳, 宇田川 玲, 浅井 哲也, 雨宮 好仁, "確率共鳴を利用した低消費電力 SRAM に関する考察," 電子情報通信学会総合大会, (仙台), 2010年3月.
[details]Thu, 7 Jan 2010 17:32:08 +0900

On-chip PVT compensation technique (Journal Paper)
Tsugita Y., Ueno K., Hirose T., Asai T., and Amemiya Y., "An on-chip PVT compensation technique with current monitoring circuit for low-voltage CMOS digital LSIs," IEICE Transactions on Electronics, vol. E93-C, no. 6 (2010), in press.
[details]Wed, 9 Dec 2009 09:40:26 +0900

Best Paper Award (2009 IEEJ Analog VLSI Workshop)
Ueno K., Asai T., and Amemiya Y., "A 0.02-to-2-MHz tunable clock reference circuit for intermittent pulse generators," 2009 IEEJ International Analog VLSI Workshop Best Paper Award, Nov. 2009.
[details]Tue, 24 Nov 2009 13:57:24 +0900

Neuromorphic Information Processing (NLP, Nov 2008)
佐橋 透, 宇田川 玲, 浅井 哲也, 雨宮 好仁, "ばらつきを含む多層ニューラルネットワークモデルにおける確率共鳴の理論解析," 電子情報通信学会 非線形問題研究会, (屋久島), 2009年11月.
藤田 大地, 浅井 哲也, 雨宮 好仁, "弱電気魚の混信回避行動モデルに基づく周波数比較器〜振幅/位相情報から周波数の高低を判断するCMOS回路の設計〜," 電子情報通信学会 非線形問題研究会, (屋久島), 2009年11月.
[details]Wed, 4 Nov 2009 12:55:19 +0900

Offset-cancelled subthreshold CMOS Amplifier (ICECS 2009)
Iida T., Asai T., Sano E., and Amemiya Y., "Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers," The 16th IEEE International Conference on Electronics, Circuits, and Systems, Hammamet, Tunisia (Dec. 13-16, 2009).
[details]Sat, 17 Oct 2009 14:28:09 +0900

Subthreshold CMOS gadgets (ICD, Dec 2009)
松下 拓道, 上野 憲一, 浅井 哲也, 雨宮 好仁, "極低電力LSIのための間欠パルス回路," 電子情報通信学会 集積回路研究会, (静岡), 2009年12月.
山本 和輝, 上野 憲一, 浅井 哲也, 雨宮 好仁, "サブスレッショルドCMOS LSIのためのナノワットDA変換器," 電子情報通信学会 集積回路研究会, (静岡), 2009年12月.
[details]Tue, 13 Oct 2009 16:13:14 +0900

Subthreshold CMOS LSIs (ECT, Oct 2009)
上野 憲一, 廣瀬 哲也, 浅井 哲也, 雨宮 好仁, "極低消費電力LSIのためのCMOS参照電流源回路," 電気学会-電子回路研究会, (宮崎), 2009年10月.
浅井 慎一, 上野 憲一, 浅井 哲也, 雨宮 好仁, "サブスレッショルドCMOS差動対による高抵抗デバイス," 電気学会-電子回路研究会, (宮崎), 2009年10月.
[details]Tue, 15 Sep 2009 18:31:46 +0900

Floating millivolt reference for PTAT current generation (Journal Letter)
上野 憲一, 廣瀬 哲也, 浅井 哲也, 雨宮 好仁, "サブスレッショルドMOSFETを用いたPTAT電流生成のための微小フローティング電圧源回路," 映像情報メディア学会誌, in press.
[details]Mon, 7 Sep 2009 14:52:01 +0900

Process compensation techniques for low-voltage CMOS digital circuits (Journal Letter)
次田 祐輔, 廣瀬 哲也, 上野 憲一, 浅井 哲也, 雨宮 好仁, "低電圧CMOSディジタル回路のプロセスバラツキ補正技術," 映像情報メディア学会誌, in press.
[details]Wed, 2 Sep 2009 15:00:25 +0900

Brain-inspired electrical circuits: life and research in Japan (Special Lecture)
Tovar G.M., "Brain-inspired electrical circuits: life and research in Japan," Special Lecture in School of Electronics Engineering, Jose Antonio Paez University, Valencia, Venezuela (Sep. 21, 2009).
[details]Wed, 2 Sep 2009 14:54:54 +0900

Noise-driven neuromorphic single-electron circuits (Invited Talk)
Kikombo A.K., Asai T. and Amemiya Y., "Neuro-morphic circuit architectures employing temporal noises and device fluctuations to enhance signal-to-noise ratio in pulse-density modulation," The 4th International Workshop on Natural Computing, Himeji, Japan (Sep. 23-25, 2009).
[details]Wed, 2 Sep 2009 14:49:59 +0900

Towards ReRAM Neural Network LSI (JNNS, Sep. 2009)
赤穂 伸雄, 浅井 哲也, 柳田 剛, 川合 知二, 雨宮 好仁, "抵抗変化型メモリをシナプスとして利用したニューラルネット集積回路に関する考察," 日本神経回路学会 第19回全国大会, (仙台), 2009年9月.
[details]Tue, 1 Sep 2009 12:08:00 +0900

Voltage and Current Reference Circuits (Book Chapter)
Ueno K., "CMOS voltage and current reference circuits consisting of subthreshold MOSFETs --Micropower circuit components for power-aware LSI applications--," Solid State Circuits Technologies, Kordic V., Ed., In-tech (2009), in press.
[details]Thu, 27 Aug 2009 16:11:00 +0900

Single-electron photon-positioning sensor (Nanotechnology; Journal Paper)
Kikombo A.K., Tabe M., and Amemiya Y., "Photon position sensor consisting of single-electron circuits," Nanotechnology, in press.
[details]Thu, 20 Aug 2009 09:55:00 +0900

Single-electron PDM circuits exploiting noises (ICONIP 2009)
Kikombo A.K., Asai T, Amemiya Y., "Exploiting temporal noises and device fluctuations in enhancing fidelity of pulse-density modulator consisting of single-electron neural circuits," The 16th International Conference on Neural Information Processing, Bangkok, Thailand (Dec. 1-5, 2009).
[details]Wed, 19 Aug 2009 09:52:00 +0900

Tunable clock reference circuit (Analog VLSI WS 2009)
Ueno K., Asai T., and Amemiya Y., "A 0.02-to-2-MHz tunable clock reference circuit for intermittent pulse generators," 2009 IEEJ International Analog VLSI Workshop, Chiangmai, Thailand (Nov. 18-20, 2009).
[details]Tue, 18 Aug 2009 09:48:00 +0900

Neuromorphic STDP CMOS circuits (Book Chapter)
Tovar G.M., Asai T., and Amemiya Y., "Noise-tolerant analog circuits for sensory segmentation based on symmetric STDP learning," Advances in Neuro-Information Processing, Koppen M., Kasabov N., and Coghill G, Eds., Lecture Notes in Computer Science, vol. 5507, pp. 851-858, Springer, Berlin / Heidelberg (2009).
[details]Tue, 4 Aug 2009 15:12:53 +0900

Low-voltage process-compensated VCO (IEICE; Journal Paper)
Ueno K., Hirose T., Asai T., and Amemiya Y., "Low-voltage process-compensated VCO with on-chip process monitoring and body-biasing circuit techniques," IEICE Transactions on Fundamentals of Electronics, Communications and Computer, vol. E92-A, (2009), in press.
[details]Tue, 4 Aug 2009 15:07:34 +0900

CMOS clock reference circuit (ICD, Oct. 2009)
上野 憲一, 浅井 哲也, 雨宮 好仁, "周波数同期技術を用いたオンチップCMOS参照クロック源回路," 電子情報通信学会 集積回路研究会, (東京), 2009年10月.
[details]Tue, 28 Jul 2009 15:19:31 +0900

High-speed Single-Electron PDM Circuits (Nano-Net 2009)
Kikombo A.K., Asai T, Amemiya Y., "Pulse-density modulation with an ensemble of single-electron circuits employing neuronal heterogeneity to achieve high temporal resolution," The 4th International Conference on Nano-Networks, Luzern, Switzerland (Oct. 18-20, 2009).
[details]Thu, 16 Jul 2009 12:01:50 +0900

Can we utilize ReRAMs in neural network hardware? (BrainIS)
赤穂 伸雄, 浅井 哲也, 雨宮 好仁, "ニューラルネットワークハードウェアにおける抵抗変化型メモリの積極的利用に関する一考察," Brain inspired-system研究会, (北九州), 2009年9月.
[details]Thu, 9 Jul 2009 12:11:39 +0900

Analog CMOS gadgets (IEICE, Sep., 2009)
赤穂 伸雄, 浅井 哲也, 柳田 剛, 川合 知二, 雨宮 好仁, "ユニポーラReRAMの簡易SPICEモデル," 電子情報通信学会ソサイエティ大会, (新潟), 2009年9月.
嶋田 英人, 上野 憲一, 浅井 哲也, 雨宮 好仁, "サブスレッショルドLSIのためのオンチップ電源〜スイッチングレギュレータとシリーズレギュレータの比較〜," 電子情報通信学会ソサイエティ大会, (新潟), 2009年9月.
松下 拓道, 上野 憲一, 浅井 哲也, 雨宮 好仁, "サブスレッショルドCMOS回路による間欠動作スイッチ," 電子情報通信学会ソサイエティ大会, (新潟), 2009年9月.
山本 和輝, 飯田 智貴, 浅井 哲也, 雨宮 好仁, "サブスレッショルドMOS回路のためのナノアンペア電流源," 電子情報通信学会ソサイエティ大会, (新潟), 2009年9月.
[details]Thu, 9 Jul 2009 11:40:13 +0900

2009 CMOS Emerging Technologies Workshop (Invited Talk)
Ueno K., "Micropower LSIs consisting of subthreshold CMOS circuits for smart sensor applications," 2009 CMOS Emerging Technologies Workshop: Research & Business Opportunities Ahead, Vancouver, Canada (Sep. 23-25, 2009).
[details]Fri, 26 Jun 2009 18:16:39 +0900

Young researcher's award, IEEE SSCS Japan Chapter
上野 憲一, "LSI設計を通した研究の進め方 〜雨宮研究室の設計事例を通して〜," VDECデザイナーフォーラム2009 - IEEE SSCS Japan Chapter Young Researcher Award, Jun. 2009.
[details]Tue, 9 Jun 2009 16:59:33 +0900

Analog/digital CMOS gadgets (VDEC Designer's Forum 2008)
上野 憲一, "LSI設計を通した研究の進め方 〜雨宮研究室の設計事例を通して〜," VDECデザイナーフォーラム2009, S-06, (東京), 2009年6月.
浅井 慎一, 上野 憲一, 浅井 哲也, 雨宮 好仁, "温度変化を補償したサブスレッショルドCMOS高抵抗回路," VDECデザイナーフォーラム2009, P-18, (東京), 2009年6月.
飯田 智貴, 浅井 哲也, 佐野 栄一, 雨宮 好仁, "サブスレッショルドCMOSオペアンプによるレベルシフト回路," VDECデザイナーフォーラム2009, P-19, (東京), 2009年6月.
嶋田 英人, 上野 憲一, 浅井 哲也, 佐野 栄一, 雨宮 好仁, "0.5V動作LSIのためのオンチップ電源," VDECデザイナーフォーラム2009, P-20, (東京), 2009年6月.
[details]Thu, 4 Jun 2009 16:56:00 +0900

Stochastic resonance with population heterogeneity (IEICE; Journal Paper)
Utagawa A., Sahashi T., Asai T., and Amemiya Y., "Stochastic resonance in an array of locally-coupled McCulloch-Pitts neurons with population heterogeneity," IEICE Transactions on Fundamentals of Electronics, Communications and Computer, vol. E92-A, (2009), in press.
[details]Wed, 3 Jun 2009 19:11:56 +0900

Subthreshold analog CMOS gadgets (ITC-CSCC 2009)
Ueno K., Asai T., and Amemiya Y., "A 30-MHz 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop," The 35th European Solid-State Circuits Conference, Athens, Greece (Sep. 14-18, 2009).
Ueno K., Asai T., and Amemiya Y., "A PTAT voltage source consisting of subthreshold MOSFETs for temperature sensor LSIs," The 24th International Technical Conference on Circuits/Systems, Computers and Communications, Jeju Island, Korea (Jul. 5-8, 2009).
Iida T., Asai T., Sano E., and Amemiya Y., "Level-shift circuit using subthreshold-operated CMOS operational amplifiers ," The 24th International Technical Conference on Circuits/Systems, Computers and Communications, Jeju Island, Korea (Jul. 5-8, 2009).
[details]Fri, 29 May 2009 17:30:14 +0900

A fully-integrated clock reference with frequency-locked loop (ESSCIRC 2009)
Ueno K., Asai T., and Amemiya Y., "A 30-MHz 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop," The 35th European Solid-State Circuits Conference, Athens, Greece (Sep. 14-18, 2009).
[details]Mon, 25 May 2009 14:12:48 +0900

Phase-shift oscillator based on heat conduction (JCSC; Journal Paper)
Hirai T., Asai T., and Amemiya Y., "CMOS phase-shift oscillator based on the conduction of heat," Journal of Circuits, Systems, and Computers, (2009), in press.
[details]Thu, 7 May 2009 11:19:54 +0900

Subthreshold CMOS gadgets (WS for LSIs and Systems, May 2009)
飯田 智貴, 浅井 哲也, 雨宮 好仁, "サブスレッショルドCMOS演算増幅器とその応用," LSIとシステムのワークショップ2009, (北九州), 2009年5月.
次田 祐輔, 上野 憲一, 廣瀬 哲也, 浅井 哲也, 雨宮 好仁, "低電圧CMOSディジタル集積回路のためのPVTバラツキ補償技術," LSIとシステムのワークショップ2009, (北九州), 2009年5月.
嶋田 英人, 上野 憲一, 浅井 哲也, 雨宮 好仁, "サブスレッショルドCMOSディジタル化色のためのオンチップ電源," LSIとシステムのワークショップ2009, (北九州), 2009年5月.
[details]Mon, 13 Apr 2009 13:26:19 +0900

Experimental noise-induced phase synchronization (NDES 2009)
Utagawa A., Asai T., and Amemiya Y., "Noise-induced phase synchronization among analogue oscillator circuits: Experimental results with discrete MOS devices," The 17th International Workshop on Nonlinear Dynamics of Electronic Systems, Rapperswil, Switzerland (Jun. 21-24, 2009).
[details]Wed, 1 Apr 2009 14:31:33 +0900

High-fidelity neuromorphic CMOS circuits (ICCNS 2009)
Utagawa A., Asai T., and Amemiya Y., "High-fidelity neuromorphic pulse-sendity modulator based on a model of vestibulo-ocular reflex," 12th International Conference on Cognitive and Neural Systems, Boston, USA (May 27-30, 2009).
[details]Mon, 9 Mar 2009 10:11:44 +0900

A CMOS voltage reference (JSCC; Journal Paper)
Ueno K., Hirose T., Asai T., and Amemiya Y., "A 300-nW, 7-ppm/°C, 20-ppm/V CMOS voltage reference circuit consisting of subthreshold MOSFETs," IEEE Journal of Solid-State Circuits, vol. 44, (2009), in press.
[details]Fri, 6 Mar 2009 14:03:58 +0900

NCSP 2009 student paper awards
Sahashi T., Utagawa A., Asai T., and Amemiya Y., "Theoretical analysis of collective stochastic resonance with population heterogeneity," The Research Institute of Signal Processing - NSCP'09 Student Paper Award, Mar. 2009.
Fujita D., Asai T., and Amemiya Y., "A CMOS frequency comparator based on jamming avoidance response of Eigenmannia," The Research Institute of Signal Processing - NSCP'09 Student Paper Award, Mar. 2009.
[details]Fri, 6 Mar 2009 10:03:01 +0900

Subthreshold CMOS Gadgets (KWS, May 2009)
上野 憲一, 浅井 哲也, 雨宮 好仁, "MOSFETのサブスレッショルド特性を利用したPTATクロックパルス発生回路," 第22回 回路とシステム軽井沢ワークショップ, (長野), 2009年4月.
飯田 智貴, 浅井 哲也, 雨宮 好仁, "サブスレッショルドCMOS演算増幅器による大容量キャパシタ等価素子," 第22回 回路とシステム軽井沢ワークショップ, (長野), 2009年4月.
嶋田 英人, 上野 憲一, 浅井 哲也, 雨宮 好仁, "サブスレッショルドCMOS論理システムのための電源回路," 第22回 回路とシステム軽井沢ワークショップ, (長野), 2009年4月.
[details]Thu, 26 Feb 2009 18:12:14 +0900

Subthreshold voltage reference (IEICE Silicon Analog RF, Mar. 2009)
上野 憲一, 廣瀬 哲也, 浅井 哲也, 雨宮 好仁, "サブスレッショルドLSIのための極低消費電力バンドギャップ参照電圧源回路," 電子情報通信学会 シリコンアナログRF研究会, (東京), 2009年3月.
[details]Mon, 23 Feb 2009 12:54:46 +0900

Temperature-to-frequency converter (IEEE Transducers 2009)
Ueno K., Asai T., and Amemiya Y., "Temperature-to-frequency converter consisting of subthreshold MOSFET circuits for smart temperature-sensor LSIs," The 15th International Conference on Solid-State Sensors, Actuators and Microsystems, Denver, USA (Jun. 21-25, 2009).
[details]Fri, 20 Feb 2009 15:22:31 +0900

Noise-shaping single-electron circuit (IJCNN 2009)
Kikombo A.K., Asai T., Oya T., Schmid A., Leblebici Y., and Amemiya Y., "A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons," 2009 International Joint Conference on Neural Networks, Atlanta, USA (Jun. 14-19, 2009).
[details]Mon, 9 Feb 2009 08:38:23 +0900

Subthreshold CMOS LSIs (ISCAS 2009)
Ueno K., Asai T., and Amemiya Y., "Low-power clock reference circuit for intermittent operation of subthreshold LSIs," 2009 International Symposium on Circuits and Systems, Taipei, Taiwan (May 24-27, 2009).
Tsugita Y., Ueno K., Hirose T., Asai T., and Amemiya Y., "On-chip PVT compensation techniques for low-voltage CMOS digital LSIs," 2009 International Symposium on Circuits and Systems, Taipei, Taiwan (May 24-27, 2009).
[details]Fri, 9 Jan 2009 14:57:32 +0900

High-fidelity neuromorphic pulse-density modulator (JPS, Mar. 2009)
浅井 哲也, 宇田川 玲, 雨宮 好仁, "雑音を利用してパルス密度変調を行う神経模倣ハードウェア," 日本物理学会第64回年次大会, (東京), 2009年3月.
[details]Thu, 8 Jan 2009 16:24:13 +0900

Digital circuits exploiting collision-based fusion gates (ISMAC 2009)
Yamada K., Asai T., and Amemiya Y., "Towards compact low-power digital circuits exploiting collision-based fusion gates," 2009 International Symposium on Multimedia and Communication Technology, Bangkok, Thailand (Jan. 22-23, 2009).
[details]Wed, 7 Jan 2009 18:17:18 +0900

Subthreshold CMOS gadgets (IEICE, Mar., 2009)
上野 憲一, 浅井 哲也, 雨宮 好仁, "サブスレッショルドCMOS回路を用いたPTATクロックパルス発生器," 電子情報通信学会総合大会, (松山), 2009年3月.
浅井 慎一, 上野 憲一, 浅井 哲也, 雨宮 好仁, "温度依存性を考慮したサブスレッショルドCMOS高抵抗回路," 電子情報通信学会総合大会, (松山), 2009年3月.
飯田 智貴, 浅井 哲也, 雨宮 好仁, "サブスレッショルドCMOS演算増幅器によるオフセット補償回路," 電子情報通信学会総合大会, (松山), 2009年3月.
佐橋 透, 宇田川 玲, 浅井 哲也, 雨宮 好仁, "空間ばらつきを持つ受容野モデルにおける確率共鳴の理論解析," 電子情報通信学会総合大会, (松山), 2009年3月.
次田 祐輔, 上野 憲一, 廣瀬 哲也, 浅井 哲也, 雨宮 好仁, "CMOSディジタルシステムのためのPVTバラツキ補正回路," 電子情報通信学会総合大会, (松山), 2009年3月.
藤田 大地, 浅井 哲也, 雨宮 好仁, "弱電気魚のジャミング回避行動モデルに基づくCMOS周波数比較器," 電子情報通信学会総合大会, (松山), 2009年3月.
赤穂 伸雄, 浅井 哲也, 雨宮 好仁, "視覚野の階層構造を模擬したパターン認識処理を行うアナログCMOS回路," 電子情報通信学会総合大会, (松山), 2009年3月.
嶋田 英人, 上野 憲一, 浅井 哲也, 雨宮 好仁, "サブスレッショルドCMOS論理システムのための電源回路," 電子情報通信学会総合大会, (松山), 2009年3月.
[details]Wed, 7 Jan 2009 18:12:52 +0900

An Ultra-low Power Clock Reference (ISMAC 2009)
Ueno K., Asai T., and Amemiya Y., "An ultra-low power clock reference generator for subthreshold LSIs," 2009 International Symposium on Multimedia and Communication Technology, Bangkok, Thailand (Jan. 22-23, 2009).
[details]Fri, 2 Jan 2009 15:21:00 +0900

Neuromorphic VLSI gadgets (NCSP 2009)
Utagawa A., Asai T., and Amemiya Y., "High-fidelity pulse-density modulation with noisy neuromorphic circuits based on a model of vestibulo-ocular reflex," 2009 RISP International Workshop on Nonlinear Circuits and Signal Processing, Honolulu, USA (Mar. 1-3, 2009).
Sahashi T., Utagawa A., Asai T., and Amemiya Y., "Theoretical analysis of collective stochastic resonance with population heterogeneity," 2009 RISP International Workshop on Nonlinear Circuits and Signal Processing, Honolulu, USA (Mar. 1-3, 2009).
Fujita D., Asai T., and Amemiya Y., "A CMOS frequency comparator based on jamming avoidance response of Eigenmannia," 2009 RISP International Workshop on Nonlinear Circuits and Signal Processing, Honolulu, USA (Mar. 1-3, 2009).
[details]Thu, 1 Jan 2009 15:16:00 +0900

Single-erectron circuits for edge detection (Journal Paper)
Kikombo A.K., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "A Bio-inspired image processor for edge detection with single-erectron circuits," Journal of Signal Processing, vol. 13, no. 1, (2009), in press.
[details]Thu, 20 Nov 2008 12:29:50 +0900

Fault-tolerant neural nets (ICONIP 2008)
Kikombo A.K., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "Fault-tolerant architectures for nanoelectronic circuits employing simple feed-forward neural networks without learning," The 15th International Conference on Neural Information Processing of the Asia-Pacific Neural Network Assembly, Auckland, New Zealand (Nov. 25-28, 2008).
[details]Wed, 5 Nov 2008 10:14:26 +0900

Noise-shaping single-electron circuits (Journal Paper)
Kikombo A.K, Asai T., Oya T., Schmid A., Leblebici Y., and Amemiya Y., "A neuromorphic single-electron circuit for noise-shaping pulse-density modulation," International Journal of Nanotechnology and Molecular Computation, vol. 1, no. 2, (2009), in press.
[details]Wed, 29 Oct 2008 17:18:15 +0900

SFQ circuits for unconventional computing (SICE 2008)
Yamada K., Asai T., and Amemiya Y., "Single-flux quantum circuits for digital cellular automata and analog reaction-diffusion computing," SICE Symposium on Systems and Information, Himeji, Japan (Nov. 26-28, 2008).
[details]Fri, 17 Oct 2008 16:25:00 +0900

Threshold logics for subthreshold CMOS circuits (Journal Paper)
Ogawa T., Hirose T., Asai T., and Amemiya Y., "Threshold logic systems consisting of subthreshold CMOS circuits," IEICE Transactions on Fundamentals of Electronics, Communications and Computer, vol. E92-A, no. 2, (2009), in press.
[details]Wed, 15 Oct 2008 18:27:00 +0900

Temporal-coding neuromorphic CMOS circuits (Journal Paper)
Tovar G.M., Asai T., Fujita D., and Amemiya Y., "Analog MOS circuits implementing a temporal coding neural model," Journal of Signal Processing, vol. 12, no. 6, (2008), in press.
[details]Tue, 14 Oct 2008 18:19:00 +0900

Noise-tolerant neuromorphic CMOS circuits (ICONIP 2008)
Tovar G.M., Asai T., and Amemiya Y., "Noise-tolerant analog circuits for sensory segmentation based on symmetric STDP learning," The 15th International Conference on Neural Information Processing of the Asia-Pacific Neural Network Assembly, Auckland, New Zealand (Nov. 25-28, 2008).
[details]Mon, 6 Oct 2008 15:16:00 +0900

Voltage reference based on subthreshold MOSFETs (ASP-DAC 2009)
Ueno K., Hirose T., Asai T., and Amemiya Y., "A 300 nW, 7 ppm/°C CMOS voltage reference circuit based on subthreshold MOSFETs," The 14th Asia and South Pacific Design Automation Conference, Yokohama, Japan (Jan. 19-22, 2009).
[details]Mon, 29 Sep 2008 11:52:00 +0900

Nature-inspired single-electron circuits (Book Chapter)
Asai T. and Oya T., "Nature-inspired single-electron circuits," Artificial Life Models in Hardware, Adamatzky A. and Komosinski M., Eds., Springer, in press.
[details]Fri, 19 Sep 2008 12:59:00 +0900

Subthreshold CMOS gadgets (IEICE, ICD, Oct., 2008)
Ueno K., Hirose T., Asai T., Amemiya Y., "An ultra-low power voltage reference circuit consisting of subthreshold MOSFETs ," IEICE Workshop of ICD, (Sapporo), Oct., 2008.
Tsugita Y., Ueno K., Hirose T., Asai T., Amemiya Y., "低電圧CMOSディジタル回路の特性バラツキ補償技術の構築 ," IEICE Workshop of ICD, (Sapporo), Oct., 2008.
[details]Tue, 2 Sep 2008 11:11:32 +0900

Single-electron circuits for dendritic pattern generation (Book Chapter)
Motoike I.N., Asai T., "Self-organizing dendritic trees implemented on single-electron devices," Topology Designing, Bookers Ltd. Ed., NTS Publishing, Tokyo (2009).
[details]Wed, 27 Aug 2008 10:05:47 +0900

Thermosensing CMOS circuit (Journal Paper)
Hirose T., Hagiwara A., Asai T., and Amemiya Y., "A highly sensitive thermosensing CMOS circuit based on self-biasing circuit technique," IEEJ Transactions on Electrical and Electronic Engineering, vol. 4, no. 2, (2009), in press.
[details]Wed, 27 Aug 2008 09:54:18 +0900

SFQ circuits for digital CA and analog RD computing (IWNC 2008)
Yamada K., Asai T., and Amemiya Y., "Single-flux quantum circuits for digital cellular automata and analog reaction-diffusion computing," The 3rd International Workshop on Natural Computing, Yokohama, Japan (Sep. 23, 2008).
[details]Tue, 26 Aug 2008 12:40:01 +0900

Neuromorphic systems and circuits (JNNS 2008)
Utagawa A., Asai T., Amemiya Y., "Real-world experiments for noise-induced synchronization among noisy electric neuron circuits," The 18th Annual Conference of Japanese Neural Network Society, P2-6, (Tsukuda), Sep., 2008.
Sahashi T., Utagawa A., Asai T., Amemiya Y., "Stochastic resonance in a simple receptive-field model with nonidentical noisy photoreceptors," The 18th Annual Conference of Japanese Neural Network Society, P2-25, (Tsukuda), Sep., 2008.
Fujita D., Tovar G.M., Asai T., Amemiya Y., "Storage capacities of temporal-coding neural hardware," The 18th Annual Conference of Japanese Neural Network Society, P1-26, (Tsukuda), Sep., 2008.
[details]Tue, 26 Aug 2008 12:33:08 +0900

SFQ dual-rail logic circuits based on asynchronous CBC (ISS 2008)
Yamada K., Asai T. and Amemiya Y., "Single-flux-quantum dual-rail logic circuits with asynchronous collision-based fusion gates," 21st International Symposium on Superconductivity, FDP-26, Tsukuba, Japan (Oct. 27-29, 2008).
[details]Tue, 5 Aug 2008 18:06:56 +0900

Process compensated current reference (ASSCC 2008)
Ueno K., Hirose T., Asai T., and Amemiya Y., "A 46-ppm/°C temperature and process compensated current reference with on-chip threshold voltage monitoring circuit," IEEE Asian Solid-State Circuits Conference 2008, Fukuoka, Japan (Nov. 3-5, 2008).
[details]Thu, 31 Jul 2008 18:24:22 +0900

Subthreshold CMOS / SFQ gadgets (IEICE, Sep., 2008)
Yamada K., Asai T., Amemiya Y., "Asynchronous single-flux quantum logic circuit based on collision-based computing," IEICE Society Conference, (Kawasaki), Sep., 2008.
Ogawa T., Ueno K., Shimada H., Asai T., Amemiya Y., "Effects of MOSFET threshold voltage on operation of subthreshold CMOS logic circuits," IEICE Society Conference, (Kawasaki), Sep., 2008.
Hirai T., Asai T., Amemiya Y., "Heat conduction phase-shift oscillator using poly-silicon temperature sensor," IEICE Society Conference, (Kawasaki), Sep., 2008.
Asai S., Ueno K., Asai T., Amemiya Y., "High resistance resistor consisting of a subthreshold-operated differential pair," IEICE Society Conference, (Kawasaki), Sep., 2008.
Iida T., Asai T., Amemiya Y., "High-pass filter circuit that uses subthreshold CMOS operational amplifiers," IEICE Society Conference, (Kawasaki), Sep., 2008.
Tsugita Y., Ueno K., Hirose T., Asai T., Amemiya Y., "Process and temperature compensation techniques for low-voltage CMOS digital circuits," IEICE Society Conference, (Kawasaki), Sep., 2008.
[details]Mon, 14 Jul 2008 17:10:47 +0900

Single-electron circuits for motion detection (Journal Paper)
Kikombo A.K., Asai T., and Amemiya Y., "An elementary neuro-morphic circuit for visual motion detection with single-electron devices based on correlation neural networks," Journal of Computational and Theoretical Nanoscience, (2008), in press.
[details]Fri, 11 Jul 2008 05:43:19 +0900

Current reference circuit for subthreshold CMOS LSIs (SSDM 2008)
Ueno K., Asai T., and Amemiya Y., "Current reference circuit for subthreshold CMOS LSIs," 2008 International Conference on Solid State Devices and Materials, Ibaraki, Japan (Sep. 23-26, 2008).
[details]Thu, 3 Jul 2008 11:54:36 +0900

Stochastic resonance in retinomorphic neural networks (NOLTA 2008)
Utagawa A., Asai T., Sahashi T., and Amemiya Y., "Stochastic resonance in retinomorphic neural networks with nonidentical photoreceptors and noisy McCulloch-Pitts neurons," 2008 International Symposium on Nonlinear Theory and its Applications, Budapest, Republic of Hungary (Sep. 7-10, 2008).
[details]Mon, 16 Jun 2008 11:55:22 +0900

CMOS oscillator and single-electron vision chips (AWAD 2008)
Hirai T., Asai T., and Amemiya Y., "CMOS phase-shift oscillator using the conduction of heat," 2008 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Sapporo, Japan (Jul. 9-11, 2008).
Kikombo A.K., Asai T., and Amemiya Y., "An insect vision-based single-electron circuit performing motion detection," 2008 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Sapporo, Japan (Jul. 9-11, 2008).
[details]Tue, 3 Jun 2008 13:49:52 +0900

Circuit implementation of historic analog cellular automata (NDES 2008)
Kawabata K., Asai T., Amemiya Y., "Circuit implementation of historic analog cellular automata based on Wolfram's rule 90/150," The Physical Society of Japan 2008 Autumn Meeting , (Iwate), Sept., 2008.
[details]Mon, 2 Jun 2008 16:38:15 +0900

Analog/digital CMOS gadgets (VDEC Designer's Forum 2008)
Utagawa A., Asai T., Amemiya Y., "アナログCMOS振動子群の雑音による位相同期手法," VDECデザイナーフォーラム2008, P-01, (東京), 2008年6月.
Tsugita Y., Ueno K., Hirose T., Asai T., Amemiya Y., "低電圧CMOSディジタル回路のプロセス・温度バラツキ補正アーキテクチャ構築," VDECデザイナーフォーラム2008, P-02, (東京), 2008年6月.
Sahashi T., Utagawa A., Asai T., Hirose T., Amemiya Y., "しきい素子を利用した確率共鳴現象の回路実験," VDECデザイナーフォーラム2008, P-03, (東京), 2008年6月.
Fujita D., Tovar G.M., Asai T., Amemiya Y., "時系列コーディングを行う生体様CMOSアナログ回路," VDECデザイナーフォーラム2008, P-04, (東京), 2008年6月.
Asai S., Ueno K., Asai T., Amemiya Y., "サブスレッショルドCMOS回路による高抵抗の生成," VDECデザイナーフォーラム2008, P-05, (東京), 2008年6月.
Ogawa T.，Hirose T.，Asai T.，Amemiya Y., "サブスレッショルド領域におけるCMOSディジタル回路動作の解析," VDECデザイナーフォーラム2008, P-06, (東京), 2008年6月.
Hirai T.，Asai T.，Amemiya Y., "熱伝導を利用したCMOS移相発振器," VDECデザイナーフォーラム2008, P-07, (東京), 2008年6月.
Iida T.，Asai T.，Amemiya Y., "サブスレッショルドCMOSオペアンプを用いたオフセット電圧補正技術," VDECデザイナーフォーラム2008, P-08, (東京), 2008年6月.
Ueno K., Hirose T., Asai T., Amemiya Y., "CMOSアナログ回路のチップ間特性バラツキ補正技術のための参照電圧源," VDECデザイナーフォーラム2008, P-09, (東京), 2008年6月.
[details]Mon, 2 Jun 2008 16:37:23 +0900

CMOS voltage reference circuit for on-chip process monitoring (ESSCIRC 2008)
Ueno K., Hirose T., Asai T., and Amemiya Y., "A 0.3-µW, 7 ppm / °C CMOS voltage reference circuit for on-chip process monitoring in analog circuits," The 34th European Solid-State Circuits Conference, Edinburgh, U.K. (Sep. 15-19, 2008).
[details]Fri, 23 May 2008 11:15:04 +0900

SFQ circuits with asynchronous collision-based fusion gates (ITC-CSCC 2008)
Yamada K., Asai T., and Amemiya Y., "Combinational logic computing for single-flux quantum circuits with asynchronous collision-based fusion gates," The 23rd International Technical Conference on Circuits/Systems, Computers and Communications, Shimonoseki, Japan (Jul. 6-9, 2008).
[details]Mon, 12 May 2008 11:20:31 +0900

Motion detection with single-electron devices (SNW 2008)
Kikombo A.K., Asai T., and Amemiya Y., "A neuromorphic circuit for motion detection with single-electron devices based on correlation neural networks," The 2008 IEEE Silicon Nanoelectronics Workshop, Honolulu, USA (Jun. 15-16, 2008).
[details]Mon, 21 Apr 2008 12:15:28 +0900

Historic analog cellular automata based on Wolfram's Rule 90 and 150 (NDES 2008)
Kawabata K., Asai T., Amemiya Y., "Circuit implementation of historic analog cellular automata based on Wolfram's Rule 90 and 150," 16th International Workshop on Nonlinear Dynamics of Electronic Systems, Nizhny Novgorod, Russia (Jul. 20-26, 2008).
[details]Thu, 17 Apr 2008 15:50:03 +0900

The 10th IP award (Research-Grant Section, Nikkei BP)
Ueno K., Hirose T., Asai T., Amemiya Y., "CMOSアナログ集積回路のしきい値電圧バラツキ補正のための参照電圧源回路," 第10回LSI IPデザイン・アワード 研究助成賞, 2008年4月.
[details]Thu, 10 Apr 2008 09:51:33 +0900

Noise-induced synchronization among sub-RF CMOS analog oscillators (Journal Paper)
Utagawa A., Asai T., Hirose T., and Amemiya Y., "Noise-induced synchronization among sub-RF CMOS analog oscillators for skew-free clock distribution," IEICE Transactions on Fundamentals of Electronics, Communications and Computer, vol. E91-A, no. 10, (2008), in press.
[details]Mon, 31 Mar 2008 16:34:35 +0900

Reaction-diffusion chips (Book Chapter)
Asai T., "Reaction-diffusion chip," Handbook of Self Organization, Kunitake T. Ed., Chapter 9.3.1, NTS Publishing, Tokyo (2008), in press.
[details]Mon, 31 Mar 2008 13:32:51 +0900

Morphic approaches toward establishing emerging image processing architectures (INC4)
Kikombo A.K., Asai T., and Amemiya Y., "Morphic approaches toward establishing emerging image processing architectures for Beyond CMOS nano-electronic devices," The 4th International Nanotechnology Conference on Communications and Cooperation, Tokyo, Japan (Apr. 14-17, 2008).
[details]Thu, 27 Mar 2008 10:15:29 +0900

Young researcher's award (IEICE Sapporo Section)
Utagawa A., Young researcher's award (IEICE Sapporo Section) (graduate school), Mar., 2008.
Tsugita Y., Young researcher's award (IEICE Sapporo Section) (undergraduate school), Mar., 2008.
[details]Mon, 17 Mar 2008 17:23:23 +0900

Low voltage operation of master-slave flip-flops (ICEE 2008)
Ogawa T., Hirose T., Asai T., and Amemiya Y., "Low voltage operation of master-slave flip-flops for ultra-low power subthreshold LSIs," The International Conference on Electrical Engineering 2008, Okinawa, Japan (Jul. 6-10, 2008).
[details]Mon, 3 Mar 2008 11:13:29 +0900

Edge extraction with single-slsecton devices (ICCNS 2008)
Kikombo A.K., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "Implementation of early vision model for edge extraction with single-slsecton devices," 12th International Conference on Cognitive and Neural Systems, Boston, USA (May 14-17, 2008).
[details]Fri, 29 Feb 2008 10:42:41 +0900

Temperature-compensated CMOS current reference (Journal Letter)
Hirose T., Asai T., and Amemiya Y., "Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs," IEICE Electronics Express, vol. 5, (2008), in press.
[details]Wed, 13 Feb 2008 16:05:20 +0900

Unconventional silicon microprocessors based on reaction-diffusion computing (Invited Talk)
Asai T., "Unconventional silicon microprocessors based on reaction-diffusion computing," the 12th World Multi-Conference on Systemics, Cybernetics and Informatics, Orlando, USA (Jun. 29 - Jul. 2, 2008).
[details]Mon, 28 Jan 2008 15:03:32 +0900

SFQ logic circuits exploiting collision-based fusion gates (Journal Paper)
Asai T., Yamada K., and Amemiya Y., "Single-flux quantum logic circuits exploiting collision-based fusion gates," Physica C, (2008), in press.
[details]Wed, 23 Jan 2008 15:23:10 +0900

Neuromorphic hardware utilizing fluctuations (Review)
Asai T., Utagawa A., Amemiya Y., "Neuromorphic hardware utilizing fluctuations ---noise-induced phase synchronization among on-chip clock generators---," Journal of Japanese Neural Network Society, vol. 15, no. 1, (2008), in press.
[details]Tue, 22 Jan 2008 15:31:15 +0900

Miltiplicating patterns on semiconductor reaction-diffusion systems (JPS, Mar. 2008)
Kawabata K., Asai T., Hirose T., Amemiya Y., "Multiplicating spatial patterns on semiconductor reaction-diffusion devices based on minority-carrier transport," The Physical Society of Japan 2008 Annual Meeting , (Osaka), Mar., 2008.
[details]Fri, 18 Jan 2008 16:46:03 +0900

Analog/digital CMOS gadgets and SFQ circuits (IEICE, Mar. 2008)
Ueno K., Hirose T., Asai T., Amemiya Y., "A CMOS voltage reference for process compensation in analog circuits," IEICE General Conference, (Kitakyusyu), Mar., 2008.
Yamada K., Asai T., Hirose T., Amemiya Y., "Single-flux quantum logic circuit based on collision-based computing," IEICE General Conference, (Kitakyusyu), Mar., 2008.
Ogawa T., Hirose T., Asai T., Amemiya Y., "Winner-Take-All circuits consisting of subthreshold MOS circuits," IEICE General Conference, (Kitakyusyu), Mar., 2008.
Hirai T., Hirose T., Asai T., Amemiya Y., "CMOS oscillators that make use of phase-shift in conduction of heat," IEICE General Conference, (Kitakyusyu), Mar., 2008.
Iida T., Hirose T., Asai T., Amemiya Y., "Canceling offset voltage with subthreshold MOS operational amplifiers," IEICE General Conference, (Kitakyusyu), Mar., 2008.
Sahashi T., Utagawa A., Asai T., Hirose T., Amemiya Y., "Experimental observations of stochastic resonance in electronic threshold circuit," IEICE General Conference, (Kitakyusyu), Mar., 2008.
Tsugita Y., Ueno K., Hirose T., Asai T., Amemiya Y., "Process compensation architecture for low-voltage CMOS digital circuits," IEICE General Conference, (Kitakyusyu), Mar., 2008.
Fujita D., Tovar G.M., Asai T., Hirose T., Amemiya Y., "Neuromorphic MOS circuits implementing a temporal coding neural model," IEICE General Conference, (Kitakyusyu), Mar., 2008.
[details]Thu, 10 Jan 2008 12:18:54 +0900

Emerging research architectures (Invited Talk)
Asai T., "Emerging research architectures (ERA): present and future," STRJ Workshop 2007, Tokyo, Japan (Mar. 6-7, 2008).
[details]Mon, 7 Jan 2008 13:37:20 +0900

Neuromorphic CMOS / single-electron circuits (NCSP 2008)
Kikombo A.K., Schmid A., Asai T., Leblebici Y., and Amemiya Y., "Toward a single-electron image processor for edge detection based on the inner retina model," 2008 RISP International Workshop on Nonlinear Circuits amd Signal Processing, Gold Coast, Australia (Mar. 6-8, 2008).
Utagawa A., Asai T., Hirose T., and Amemiya Y., "Noise-induced phase synchronization between nonidentical analog CMOS osscillators," 2008 RISP International Workshop on Nonlinear Circuits amd Signal Processing, Gold Coast, Australia (Mar. 6-8, 2008).
Tovar G.M., Fujita D., Asai T., Hirose T., and Amemiya Y., "Neuromorphic MOS circuits implementing a temporal coding neural model," 2008 RISP International Workshop on Nonlinear Circuits amd Signal Processing, Gold Coast, Australia (Mar. 6-8, 2008).
[details]Mon, 7 Jan 2008 11:31:10 +0900

Fingerprint image reconstruction with reaction-diffusion computers (Invited Talk)
Asai T. and Motoike I.N., "Turing-like reaction-diffusion patterns emerging on two-layered resistive sheets with nonlinear devices," The 2nd International Workshop on Natural Computing, Nagoya, Japan (Dec. 10-12, 2007).
[details]Mon, 26 Nov 2007 10:12:08 +0900

Bio-inspired single-electron circuit for early vision (ISDRS 2007)
Kikombo A.K., Schmid A., Leblebici Y., Asai T., and Amemiya Y., "A bio-inspired image processor for edge detection with single-electron circuits," International Semiconductor Device Research Symposium 2007, Maryland, USA (Dec. 12-14, 2007).
[details]Sat, 13 Oct 2007 13:49:29 +0900

Analog/digital CMOS gadgets (2007 System LSI Workshop)
Ueno K., Hirose T., Asai T., Amemiya Y., "MOSFETの特性バラツキ補正技術に向けた参照電圧源回路," 第11回システムLSIワークショップ, (北九州), 2007年11月.
Utagawa A., Asai T., Hirose T., Amemiya Y., "雑音を利用したオンチップマルチクロック源の位相同期手法," 第11回システムLSIワークショップ, (北九州), 2007年11月.
Ogawa T., Hirose T., Asai T., Amemiya Y., "低電源電圧動作時におけるマスタースレーブフリップフロップ回路の動作検討," 第11回システムLSIワークショップ, (北九州), 2007年11月.
[details]Tue, 25 Sep 2007 11:21:49 +0900

Young researcher's award, IEEE SSCS Japan Chapter
Ueno K., "ゼロから始めたLSI〜設計雨宮研究室の設計事例を通して〜," VDECデザイナーフォーラム2007 - IEEE SSCS Japan Chapter Young Researcher Award, Sep. 2007.
[details]Tue, 18 Sep 2007 14:58:41 +0900

Single-electron image processors for early vision (IEICE NC, Nov., 2007)
Kikombo Andrew Kilinga, Schmid Alexandre, Asai T., Leblebici Yusuf, Amemiya Y., "Toward a bio-inspired image processor for edge extraction with single-electron devices," IEICE Workshop of Neurocomputing, (Saga), Nov., 2007.
[details]Tue, 18 Sep 2007 14:56:16 +0900

Neuromorphic CMOS circuits for STDP learning (Journal Paper)
Fukuda E.S., Tovar G.M., Asai T., Hirose T., and Amemiya Y., "Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning," Journal of Signal Processing, (2007), in press.
[details]Fri, 14 Sep 2007 16:19:19 +0900

Neuromorphic thermosensing CMOS circuits (Journal Paper)
Tovar G.M., Asai T., Hirose T., and Amemiya Y., "Critical temperature sensor based on oscillatory neuron models," Journal of Signal Processing, (2007), in press.
[details]Wed, 12 Sep 2007 11:38:07 +0900

Analog/digital CMOS gadgets (VDEC Designer's Forum 2007)
Hirai T., Hirose T., Asai T., Amemiya Y., "熱伝導を利用した移相発振器," VDECデザイナーフォーラム2007（若手の会）, (札幌), 2007年9月.
Yamada K., Asai T., Hirose T., Amemiya Y., "Collision-based fusion gateによる組み合わせ論理回路〜小面積・低消費電力化に向けた設計手法〜," VDECデザイナーフォーラム2007（若手の会）, (札幌), 2007年9月.
Tovar G.M., Asai T., Hirose T., Amemiya Y., "Neuromorphic LSI circuits for critical temperature detection," VDECデザイナーフォーラム2007（若手の会）, (札幌), 2007年9月.
[details]Thu, 6 Sep 2007 16:44:45 +0900

Collision-based computing (CBC) with SFQ devices (ISS 2007)
Asai T. and Amemiya Y., "Single-flux quantum logic circuits exploiting collision-based fusion gates," 20th International Symposium on Superconductivity, Tsukuba, Japan (Nov. 5-7, 2007).
[details]Thu, 6 Sep 2007 12:34:02 +0900

Nonlinear dynamics of coupled single-electron oscillators (Journal Paper)
Kikombo A.K., Hirose T., Asai T., Amemiya Y., "Non-linear phenomena in electronic systems consisting of coupled single-electron oscillators," Chaos, Solitons & Fractals, in press.
[details]Thu, 23 Aug 2007 10:10:01 +0900

Threshold locgic systems (AVLSIWS 2007)
Ogawa T., Hirose T., Asai T., and Amemiya Y., "Threshold-logic systems consisting of subthreshold CMOS circuits," 2007 IEEJ International Analog VLSI Workshop, Limerick, Ireland (Nov. 7-9, 2007).
[details]Thu, 23 Aug 2007 10:07:14 +0900

VLSI Design from scratch in Amemiya Laboratory (VDEC Designer's Forum 2007)
Ueno K., "ゼロから始めたLSI設計〜雨宮研究室の設計事例を通して〜," VDECデザイナーフォーラム2007（若手の会）, (札幌), 2007年9月.
[details]Thu, 23 Aug 2007 10:04:34 +0900

Self-organizing spatial patterns on reaction-diffusion systems: Theory (Invited Talk)
Asai T., "反応拡散系における空間パターンの自己組織化とその物理," 応用物理学会 励起ナノプロセス第３回研究会励起ナノプロセス技術の将来展望, (札幌), 2007年9月.
[details]Thu, 23 Aug 2007 10:03:26 +0900

Neuromorphic CMOS Learning Circuit (ICONIP 2007)
Tovar G.M., Fukuda S.E., Asai T., Hirose T., and Amemiya Y., "Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning," 2007 International Joint Conference on Neural Networks, Florida, USA (Aug. 12-17, 2007).
[details]Mon, 6 Aug 2007 10:04:03 +0900

CMOS voltage reference / photon position detector (SSDM 2007)
Ueno K., Hirose T., Asai T., and Amemiya Y., "CMOS voltage reference based on the threshold voltage of a MOSFET," 2007 International Conference on Solid State Devices and Materials, Ibaraki, Japan (Sep. 18-21, 2007).
Kikombo A.K., Tabe M., and Amemiya Y., "Photon position detector consisting of single-electron devices," 2007 International Conference on Solid State Devices and Materials, Ibaraki, Japan (Sep. 18-21, 2007).
[details]Thu, 19 Jul 2007 10:15:11 +0900

Analog/digital CMOS gadgets and optical CBC (IEICE, Sep., 2007)
Hirai T., Hirose T., Asai T., Amemiya Y., "熱伝導による位相遅れを利用したCMOS発振回路," 電子情報通信学会ソサイエティ大会, (鳥取), 2007年9月.
Ogawa T., Hirose T., Asai T., Amemiya Y., "マスタースレーブフリップフロップ回路の低電圧動作解析," 電子情報通信学会ソサイエティ大会, (鳥取), 2007年9月.
Ueno K., Hirose T., Asai T., Amemiya Y., "サブスレッショルドCMOS回路によるしきい値電圧を参照した基準電圧源回路," 電子情報通信学会ソサイエティ大会, (鳥取), 2007年9月.
Yamada K., Asai T., 齊藤 晋聖, Hirose T., Amemiya Y., "フォトニック結晶デバイス向け組み合わせ光論理回路の設計手法," 電子情報通信学会ソサイエティ大会, (鳥取), 2007年9月.
[details]Wed, 4 Jul 2007 18:37:25 +0900

Noise-induced synchronization among CMOS oscillators (NOLTA 2007)
Utagawa A., Asai T., Hirose T., and Amemiya Y., "Noise-induced synchronization among sub-RF CMOS neural oscillators for skew-free clock distribution," 2007 International Symposium on Nonlinear Theory and its Applications (WIP session), Vancouver, Canada (Sep. 16-19, 2007).
[details]Wed, 4 Jul 2007 10:17:44 +0900

Subthreshold functional LSIs (Invited Talk)
Hirose T., "MOSFETのサブスレッショルド特性を利用した新機能LSI応用技術," IEEE Circuits and Systems Society, Kansai Chapter 講演会（サブスレッショルドLSI）, (大阪), 2007年7月.
[details]Mon, 25 Jun 2007 13:20:00 +0900

Self-organizing devices exploiting noises and fluctuations (JSAP, Sep., 2007)
Asai T., "ゆらぎを利用する自己組織化デバイス," 応用物理学会秋季大会シンポジウム講演：プログラム自己組織化を用いた分子スケールデバイス −ボトムアップ／トップダウン融合の視点から−, (札幌), 2007年9月.
[details]Mon, 18 Jun 2007 11:50:00 +0900

Photon position detector (JSAP, Sep., 2007)
Kikombo Andrew Kilinga, Amemiya Y., 田部 道晴, "単電子振動子ネットワークによるフォトン位置検出センサ," 応用物理学会秋季大会, (札幌), 2007年9月.
[details]Mon, 18 Jun 2007 11:47:59 +0900

Voltage reference circuit (IEICE, ICD, Jul., 2007)
Ueno K., Hirose T., Asai T., Amemiya Y., "MOSFETのしきい値電圧を参照した基準電圧源回路," 電子情報通信学会 集積回路研究会, (神戸), 2007年7月.
[details]Tue, 5 Jun 2007 16:54:41 +0900

Reaction diffusion semiconductor devices (JPS, Sep., 2007)

Kawabata K., Asai T., Hirose T., Amemiya Y., "少数キャリア拡散に基づく固体反応拡散系を用いたダイオード型機能素子," 日本物理学会第62回年次大会, (札幌), 2007年9月.
[details]Tue, 5 Jun 2007 16:52:20 +0900

Fault tolerant logic circuits (IEEE PRIME 2007)
Joye N., Schmid A., Leblebici Y., Asai T., and Amemiya Y., "Fault-tolerant logic gates using neuromorphic CMOS circuits," The third Conference on Ph.D. Research in Microelectronics and Electronics, Bordeaux, France (Jul. 2-5, 2007).
[details]Tue, 5 Jun 2007 16:50:49 +0900

Novel hardware for unconventional computing (Book Chapter)
Asai T., "Novel hardware for unconventional computing," Encyclopedia of Complexity and System Science, R.A. Meyers, Ed., Springer (2008) in press.
[details]Mon, 14 May 2007 12:28:18 +0900

Neuromorphic VLSI fperforming noise-shaping PDM (Journal Paper)
Utagawa A., Asai T., Hirose T., and Amemiya Y., "An inhibitory neural-network circuit exhibiting noise shaping with subthreshold MOS neuron circuits," IEICE Transactions on Fundamentals of Electronics, Communications and Computer, (2007), in press.
[details]Wed, 2 May 2007 22:57:25 +0900

Multi-valued single-electron logic circuits (SNW 2007)
Kikombo A.K., Hirose T., Asai T., and Amemiya Y., "Multi-valued logic circuits consisting of single-electron devices," 2007 Silicon Nanoelectronics Workshop, Kyoto, Japan (Jun. 10-11, 2007).
[details]Tue, 27 Mar 2007 14:15:34 +0900

Neuromorphic crcuit implementing symmetric STDP learning (IJCNN 2007)
Tovar G.M., Fukuda S.E., Asai T., Hirose T., and Amemiya Y., "Neuromorphic CMOS circuits implementing a novel neural segmentation model based on symmetric STDP learning," 2007 International Joint Conference on Neural Networks, Florida, USA (Aug. 12-17, 2007).
[details]Mon, 19 Mar 2007 10:16:15 +0900

NCSP 2007 outstanding student paper award
Utagawa A., Asai T., Hirose T., and Amemiya Y., "An inhibitory neural network circuit exhibiting noise shaping with subthreshold MOS neuron circuits," The Research Institute of Signal Processing - NSCP'07 Outstanding Student Paper Award, Mar. 2007.
[details]Tue, 6 Mar 2007 09:49:21 +0900

NCSP 2007 student paper award
Tovar G.M., Asai T., Hirose T., and Amemiya Y., "Critical temperature sensor based on spiking neuron models: experimental results with discrete MOS circuits," The Research Institute of Signal Processing - NSCP'07 Student Paper Award, Mar. 2007.
Fukuda S.E., Asai T., Hirose T., and Amemiya Y., "A novel segmentation model for neuromorphic CMOS circuits," The Research Institute of Signal Processing - NSCP'07 Student Paper Award, Mar. 2007.
[details]Tue, 6 Mar 2007 09:48:02 +0900

CMOS smart sensor (JSCC; Journal Paper)
Ueno K., Hirose T., Asai T., and Amemiya Y., "CMOS smart sensor for monitoring the quality of perishables," IEEE Journal of Solid-State Circuits, in press.
[details]Wed, 28 Feb 2007 14:31:11 +0900

Subthreshold andlog/digital CMOS gadgets (KWS 2007)
Ueno K., Hirose T., Asai T., Amemiya Y., "サブスレッショルドMOS特性を利用したPTAT電流生成のための微小フローティング電圧源回路," 第20回 回路とシステム軽井沢ワークショップ, (軽井沢), 2007年4月.
Ogawa T., Hirose T., Asai T., Amemiya Y., "サブスレッショルドMOS回路によるしきい論理システム," 第20回 回路とシステム軽井沢ワークショップ, (軽井沢), 2007年4月.
[details]Wed, 21 Feb 2007 19:19:43 +0900

Single-flux-quantum neural networks (Journal Paper)
Hirose T., Asai T., and Amemiya Y., "Pulsed neural networks consisting of single-flux-quantum spiking neurons," Physica C, (2007), in press.
[details]Tue, 6 Feb 2007 17:40:22 +0900

Neuromorphic VLSIs: past, present and future (Invited Talk)
Asai T., "Neuromorphic VLSIs: past, present and future (tentative)," 2007 Unconventional Computing, Bristol, U.K. (Jul. 12-14, 2007).
[details]Wed, 31 Jan 2007 10:25:37 +0900

Bio-inspired analog integrated circuits (Invited Seminar)
Asai T., "生物に学んだアナログ集積回路," JNNS-DEX-SMI 公開講座神経回路網の理論展開と最先端応用, (東京), 2007年3月.
[details]Tue, 23 Jan 2007 15:10:41 +0900

Analog / digital CMOS gadgets (IEICE, Mar., 2007)
Yoshii K., Asai T., Hirose T., Amemiya Y., "サブスレッショルドLSIのための基準電流源回路," 電子情報通信学会総合大会, (名古屋), 2007年3月.
Yamada K., Asai T., Hirose T., Amemiya Y., "Collision-based fusion gateの電源電圧-動作周波数特性," 電子情報通信学会総合大会, (名古屋), 2007年3月.
Ueno K., Hirose T., Asai T., Amemiya Y., "MOSFETのサブスレッショルド特性を利用したPTAT電流生成用フローティング電圧源," 電子情報通信学会総合大会, (名古屋), 2007年3月.
Ogawa T., Hirose T., Asai T., Amemiya Y., "サブスレッショルドMOS回路によるしきい論理ゲート," 電子情報通信学会総合大会, (名古屋), 2007年3月.
[details]Wed, 10 Jan 2007 18:34:12 +0900

SIngle-electron PDM circuits exploiting thermal noises (NE 2007)
Asai T., Oya T., and Amemiya Y., "Single-electron circuits performing noise-tolerant pulse-density modulation based on neuromorphic architecture," Nanotech Northern Europe 2007, Helsinki, Finland (Mar. 27-29, 2007).
[details]Tue, 9 Jan 2007 18:49:57 +0900

Multiple-valued single-electron logic circuits (JSAP, Mar., 2007)
Kikombo Andrew Kilinga, Hirose T., Asai T., Amemiya Y., "単電子の位相ロッキングを利用した多値論理回路," 応用物理学会春季大会, (神奈川), 2007年3月.
[details]Tue, 9 Jan 2007 12:03:00 +0900

Floating millivolt reference circuit (ISCAS 2007)
Ueno K., Hirose T., Asai T., and Amemiya Y., "Floating millivolt reference for PTAT current generation in subthreshold MOS LSIs," 2007 IEEE International Symposium on Circuits and Systems, New Orleans, USA (May 27-30, 2007).
[details]Tue, 9 Jan 2007 10:27:34 +0900

Neuromorpic CMOS circuits (NCSP 2007)
Utagawa A., Asai T., Hirose T., and Amemiya Y., "An inhibitory neural network circuit exhibiting noise shaping with subthreshold MOS neuron circuits," 2007 RISP International Workshop on Nonlinear Circuits amd Signal Processing, Shanghai, China (Mar. 3-6, 2007).
Tovar G.M., Asai T., Hirose T., and Amemiya Y., "Critical temperature sensor based on spiking neuron models: experimental results with discrete MOS circuits," 2007 RISP International Workshop on Nonlinear Circuits amd Signal Processing, Shanghai, China (Mar. 3-6, 2007).
Fukuda S.E., Asai T., Hirose T., and Amemiya Y., "A novel segmentation model for neuromorphic CMOS circuits," 2007 RISP International Workshop on Nonlinear Circuits amd Signal Processing, Shanghai, China (Mar. 3-6, 2007).
[details]Thu, 4 Jan 2007 12:38:55 +0900

CMOS logic circuits exploting CBC (Journal Paper)
Yamada K., Asai T., Hirose T., and Amemiya Y., "On low-power digital LSI circuits exploiting collision-based fusion gates," International Journal of Unconventional Computing, (2007), in press.
[details]Tue, 26 Dec 2006 12:47:17 +0900

Noise shaping pulse-density modulation (Book Chapter) に修士1年の宇田川君の論文が掲載決定！
Utagawa A., Asai T., Hirose T., and Amemiya Y., "Noise shaping pulse-density modulation in inhibitory neural networks with subthreshold neuron circuits," Brain-Inspired IT III, International Congress Series, Elsevier, Netherlands (2007) in press.
[details]Wed, 20 Dec 2006 15:21:26 +0900

Single-flux-quantum neural networks (IEICE, SDM, Feb. 2007)
Hirose T., Asai T., Amemiya Y., "磁束量子回路によるスパイクニューロン回路とその応用," 電子情報通信学会 電子デバイス/シリコン材料・デバイス研究会, (札幌), 2007年2月.
[details]Tue, 21 Nov 2006 13:32:33 +0900

Power-supply circuits for for subthreshold LSI (Journal Letter)
Hirose T., Asai T., and Amemiya Y., "Power-supply circuits for ultralow-power subthreshold MOS-LSIs," IEICE Electronics Express, (2006), in press.
[details]Wed, 8 Nov 2006 15:21:04 +0900

Single-flux-quantum neural networks (ISS 2006)
Hirose T., Asai T., and Amemiya Y., "Pulsed neural networks consisting of single-flux-quantum spiking neurons," The 19th International Symposium on Superconductivity, Nagoya, Japan (Oct. 30 - Nov. 1, 2006), accepted.
[details]Thu, 7 Sep 2006 18:18:03 +0900

Best paper award (UC 2006)
Yamada K., Asai T., Motoike I.N., and Amemiya Y., "On digital VLSI circuits exploiting collision-based fusion gates," Best Paper Award: International Workshop From Utopian to Genuine Unconventional Computers (UC 2006), Sep. 2006.
[details]Wed, 6 Sep 2006 17:27:34 +0900

Low power subthreshold LSIs (ISPACS 2006)
Hirose T., Asai T., Amemiya Y., "Power supply circuits for ultralow-power subthreshold CMOS smart sensor LSIs," 2006 International Symposium on Intelligent Signal Processing and Communication Systems, Tottori, Japan (Dec. 12-15, 2006), accepted.
Ueno K., Hirose T., Asai T., Amemiya Y., "Ultralow-power smart temperature sensor with subthreshold CMOS circuits," 2006 International Symposium on Intelligent Signal Processing and Communication Systems, Tottori, Japan (Dec. 12-15, 2006), accepted.
Hagiwara A., Hirose T., Asai T., Amemiya Y., "Critical temperature switch : a highly sensitive thermosensing device consisting of subthreshold MOSFET circuits," 2006 International Symposium on Intelligent Signal Processing and Communication Systems, Tottori, Japan (Dec. 12-15, 2006), accepted.
[details]Sat, 2 Sep 2006 19:26:49 +0900

Intelligent CMOS temperature sensor (System LSI Workshop 2006)
Ueno K., Hirose T., Asai T., Amemiya Y., "極低消費電力CMOSインテリジェント温度センサLSI," 第10回システムLSIワークショップ, (北九州), 2006年11月.
[details]Sat, 2 Sep 2006 19:24:33 +0900

Neuromorphic MOS circuits exhibiting precisely-timed synchronization (Journal Paper)
Tovar G.M., Hirose T., Asai T., and Amemiya Y., "Neuromorphic MOS circuits exhibiting precisely-timed synchronization with silicon spiking neurons and depressing synapses," Journal of Signal Processing, vol. 10, no. 6 (2006), in press.
[details]Wed, 30 Aug 2006 18:23:15 +0900

Analog CMOS circuit for noise shaping pulse-density modulation (JNNS 2006)
Utagawa A., Asai T., Hirose T., Amemiya Y., "サブスレッショルドVLSIニューロン回路によるノイズシェーピング・パルス密度変調," 日本神経回路学会 第16回全国大会, (名古屋), 2006年9月.
[details]Mon, 28 Aug 2006 17:41:14 +0900

CMOS temperature switch (IEICE, ICD, Aug., 2006)
Hagiwara A., Hirose T., Asai T., Amemiya Y., "サブスレッショルドMOSFETを用いた温度検出スイッチ回路," 電子情報通信学会 集積回路研究会, (札幌), 2006年8月.
[details]Tue, 25 Jul 2006 15:23:30 +0900

CMOS temperature monitor (IEICE, ICD, Aug., 2008)
Ueno K., Hirose T., Asai T., Amemiya Y., "広範囲な活性化エネルギーに適応可能なCMOS品質劣化モニタセンサLSI ," 電子情報通信学会 集積回路研究会, (札幌), 2006年8月.
[details]Tue, 25 Jul 2006 09:57:39 +0900

Reviews on single-electron circuits (Invited Paper)
(invited paper) Amemiya Y., "Single-electron logic systems based on a graphical representation of digital functions," IEICE Transactions on Electronics, vol. E89-C, no. 11, (2006), in press.
[details]Sun, 16 Jul 2006 05:39:10 +0900

Noise shaping pulse-density modulation with analog CMOS circuits (BrainIT 2006)
Utagawa A., Asai T., Hirose T., and Amemiya Y., "Noise shaping pulse-density modulation in inhibitory neural networks with noise-sensitive subthreshold neuron circuits," The 3rd International Conference of Brain-inspired Information Technology, Kitakyushu, Japan (Sep. 27-29, 2006), accepted.
[details]Sun, 16 Jul 2006 05:06:13 +0900

Analog / digital CMOS gadgets (IEICE, Sep., 2006)
Hagiwara A., Hirose T., Asai T., Amemiya Y., "温度検出スイッチ回路のしきい温度解析," 電子情報通信学会ソサイエティ大会, (金沢), 2006年9月.
Ueno K., Hirose T., Asai T., Amemiya Y., "サブスレッショルドMOSを利用したスマート温度センサLSI," 電子情報通信学会ソサイエティ大会, (金沢), 2006年9月.
Yamada K., Asai T., Hirose T., Amemiya Y., "Collision-based fusion gateを用いた16bit乗算器の設計," 電子情報通信学会ソサイエティ大会, (金沢), 2006年9月.
[details]Thu, 13 Jul 2006 12:58:02 +0900

Neuromorphic critical temperature sensor (JPS, Sep., 2006)
Asai T., Hirose T., Tovar G.M., Amemiya Y., "興奮系を用いた臨界温度センサ集積回路," 日本物理学会第62回年次大会, (千葉), 2006年9月.
[details]Mon, 3 Jul 2006 10:54:38 +0900

Coupled single-electron oscillators (JSAP, Aug., 2006)
Kikombo Andrew Kilinga, Hirose T., Asai T., Amemiya Y., "単電子結合振動子の非線形現象," 応用物理学会秋季大会, (滋賀), 2006年8月.
[details]Mon, 3 Jul 2006 10:53:29 +0900

Smart temperature sensor LSI with subthreshold CMOS devices (IEICE, ICD, Jul., 2006)
Ueno K., Hirose T., Asai T., Amemiya Y., "MOSFETのサブスレッショルド特性を利用したスマート温度センサLSIの検討," 電子情報通信学会 集積回路研究会, (静岡), 2006年7月.
[details]Mon, 3 Jul 2006 10:51:58 +0900

Neuromorphic critical temperature sensor (NOLTA 2006)
Tovar G.M., Hirose T., Asai T., and Amemiya Y.,, "Critical temperature sensor based on spiking neuron models," 2006 International Symposium on Nonlinear Theory and its Applications, Bologna, Italy (Sep. 11-14, 2006), accepted.
[details]Fri, 23 Jun 2006 13:02:41 +0900

CMOS logic circuits based on collision-based computing (Jounal Letter)
Yamada K., Motoike I.N., Asai T., and Amemiya Y., "Design methodologies for compact logic circuits based on collision-based computing," IEICE Electronics Express, (2006), in press.
[details]Thu, 15 Jun 2006 17:31:46 +0900

CMOS logic circuits based on collision-based computing (Book Chapter)
Yamada K., Asai T., Motoike I.N., and Amemiya Y., "On digital VLSI circuits exploiting collision-based fusion gates," From Utopian to Genuine Unconventional Computers, Teuscher C. and Adamatzky A., Eds., Luniver Press, U.K. (2006), in press.
[details]Thu, 8 Jun 2006 16:50:01 +0900

CMOS logic circuits based on collision-based computing (UC 2006)
Yamada K., Asai T., Motoike I.N., and Amemiya Y., "On digital VLSI circuits exploiting collision-based fusion gates," The 5th International Conference on Unconventional Computation, UC 2006, York, U.K. (Sep. 4-8, 2006), accepted.
[details]Wed, 7 Jun 2006 18:20:41 +0900

Ctirical temperature switch with subthreshold CMOS devices (Journal Letter)
Hagiwara A., Hirose T., Asai T., Amemiya Y., "弱反転MOSFETを用いた温度検出スイッチ回路," 電子情報通信学会論文誌C, vol. J88-C, no. 10 (2006), in press.
[details]Tue, 6 Jun 2006 15:53:51 +0900

Non-linear dynamical systems with single-electron oscillators (NDES 2006)
Kikombo A.K., Hirose T., Asai T., Amemiya Y., "Non-linear dynamical systems consisting of single-electron oscillators," The 14th International Workshop on Nonlinear Dynamics of Electronic Systems, Dijon, France (Jun. 6-9, 2006), accepted.
[details]Mon, 17 Apr 2006 09:40:10 +0900

The 8th IP award (Research-Grant Section, Nikkei BP)
Ueno K., Hirose T., Asai T., Amemiya Y., "広範囲な活性化エネルギーに対応可能なCMOS品質劣化モニタセンサ," 第8回LSI IPデザイン・アワード 研究助成賞, 2006年5月.
[details]Mon, 17 Apr 2006 09:21:07 +0900

CMOS reaction-diffusion device (Journal Paper)
Takahashi M., Asai T., Hirose T., and Amemiya Y, "A CMOS reaction-diffusion device using minority-carrier diffusion in semiconductors," International Journal of Bifurcation and Chaos, (2006), in press.
[details]Mon, 10 Apr 2006 15:02:01 +0900

Discrete dynamical systems with single-electron circuits (Journal Paper)
Kikombo. A.K., Oya T., Asai T., and Amemiya Y., "Discrete dynamical systems consisting of single-electron circuits," International Journal of Bifurcation and Chaos, (2006), in press.
[details]Wed, 5 Apr 2006 13:34:41 +0900

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