池辺 将之

News and Updates

2018/ 02/13A novel iris-center detection algorithm towards gaze estimation (IWMA 2018)
2018/ 01/30Sparse disparity estimation for stereo matching acceleration (ICASSP 2018)
2018/ 01/11Proto-computing architecture over a digital medium aiming at real-time video processing (Complexity)
2017/ 12/27CNN accelerator design on dynamically reconfigurable hardware platform (SASIMI 2018)
2017/ 11/17BRein memory: a reconfigurable DNN accelerator chip (IEEE JSSC)
2017/ 09/08Quantization Error-based Regularization in Neural Networks (SGAI 2017 & HENND2017)
2017/ 09/05Accelerating Deep Learning by Binarized Hardware (APSIPA ASC 2017)
2017/ 09/05Logarithmic Compression for Memory Footprint Reduction in Neural Network Training (CSA 2017)
2017/ 08/07Sign-invariant unsupervised learning for analog neural-network devices (JNNS & NOLTA 2017)
2017/ 08/04Won the best presentation award (IPSJ SIG-ARC)
2017/ 07/11Won the best presentation award (IEICE-RECONF)
2017/ 06/27Won the best presentation award (IEICE-CPSY)
2017/ 06/08Won the best presentation award (IPSJ SIG-ARC)
2017/ 05/29In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks (MWSCAS2017)
2017/ 05/29A Multithreaded CGRA for Convolutional Neural Network Processing (Circuits and Systems)
2017/ 05/06Poster presentations of image sensors and Ising machines (LSI and System Workshop 2017)
2017/ 05/01A Time-Division Multiplexing Ising Machine on FPGAs (HEART 2017)
2017/ 05/01Research presentations of deep learning and Ising machine (IEICE-RECONF/CPSY)
2017/ 05/01Accelerating ZDD Construction by Lazy Evaluation for Optimizing Memory Access Patterns (The 30th Workshop on Circuits and Systems)
2017/ 04/24A dynamic reconfigurable array accelerator for embedded microprocessor (Circuits and Systems)
2017/ 03/31A scalable ising model implementation on an FPGA (COOL Chips 20)
2017/ 03/28An energy-efficient dynamic branch predictor with naive Bayes classifier (NOLTA Journal)
2017/ 03/15Won the student paper award (NCSP 2017)
2017/ 03/14BRein memory: reconfigurable in-memory deep neural network accelerator (VLSI 2017 Symposia)
2017/ 02/06Exploring optimized accelerator design for binarizedl CNN (IJCNN 2017)
2017/ 01/12Research Trends of Hardware Deep Learning Accelerators (IEICE Synposium 2017)
2017/ 01/05Camera-position and posture estimation based on local patches of image sequences (NCSP 2017)
2016/ 12/07Low latency divider using ensemble of moving average curves (ISQED 2017)
2016/ 10/18Technical presentations at IEICE ICD/CPSY Workshop for Young Researchers
2016/ 09/22FPGA systems for super resolution and time-series forecasting (ReConFig 2016)
2016/ 08/05Reconfigurable processor array architecture for DCNN (SASIMI 2016)
2016/ 07/23Naive Bayes classifier for dynamic branch prediction (APCCAS 2016)
2016/ 07/07A hardware cellular-automaton architecture for spatial pattern generation (NOLTA 2016)
2016/ 06/13A novel iris-center detection architecture towards gaze estimation (IEICE Symposium)
2016/ 06/08Image sensor/processor 3D stacked system featuring ThruChip interfaces (ESSCIRC 2016)
2016/ 05/06FPGA-based stream processing for frequent itemset mining (J. Circuits and Systems)
2016/ 04/053D stacked imager featuring ThruChip Interfaces (ITE Trans. MTA)
2016/ 03/31Hardware-Oriented Celullar Automata for Gaze Estimation (IEICE NOLTA Society Symposium)
2016/ 03/31Presentations at IEICE LSI and Systems Workshop 2016
2015/ 03/11Image sensor/digital logic 3D stacked module (2015 VLSI Symposia)
2015/ 01/05Nonlinear Signal-Processing Gadgets (NCSP 2015)
2014/ 05/01Machine Learning of Motion Vectors exploiting High-Speed Imaging (JSP)
2014/ 04/08Presentation at LSI and Systems Workshop 2014
2014/ 03/03Won the student paper award (NCSP 2014)
2014/ 01/07FPGA implementation of a novel stereo vision algorithm (CSC 2014)
2014/ 01/06Machine Learning of Motion Vectors exploiting High-Speed Imaging (NCSP 2014)
2013/ 12/11Stereo Matching VLSI Architectures (STARC Symposium 2014)
2013/ 11/19Machine learning of motion vectors on FPGA (IEICE ICD Workshop)
2013/ 10/15Hardware-oriented stereo vision algorithm and its FPGA implementation (ICECS 2013)
2013/ 08/08Presentation: Depth map FPGA (VDEC Designer's Forum)
2013/ 05/15Award: student poster award at LSI and Systems Workshop 2013!
2013/ 04/22Jounal Paper: single-image super resolution on FPGA (J. Signal Processing)
2013/ 03/11Award: Student Paper Award (NSCP'13)
2013/ 01/03Presentation: sensor-processor 3D integration (STARC Symposium 2013)
2013/ 01/03Presentation: FPGA implementation of single-image super resolution (NCSP 2013)
2011/ 07/07Presentation: 2011 IEICE Society Conference (Sapporo, Japan)

On the development of Kansei / Intelligent Systems across Emerging Algorithms, Circuits and Devices

Masayuki Ikebe

Associate Professor (LINAS), IST, Hokkaido University
Office: IST, M-BLDG, 2F, Room M205 (TEL: +81 11-706-7689, FAX: +81 11-706-7890)
E-mail: ikebe at ist.hokudai.ac.jp

Research Topics

(UNDER CONSTRUCTION)

Academic Societies

  1. The Institute of Electronics, Information and Communication Engineers (IEICE)
  2. The Institute of Image Information and Television Engineers (ITE)

Lectures

  1. Sensing and Control Engineering (undergraduate school)
  2. Electronic Information Engineering Laboratories (undergraduate school)
  3. System Applications of VLSIs (graduate school)

Doctoral Thesis

  • Analog Integrated Circuits for Motion Detection and Visual Tracking Circuits based on Biological Vision Systems
    (edited by SIPEC / original)