高前田 伸也

News and Updates

2018/ 02/13A novel iris-center detection algorithm towards gaze estimation (IWMA 2018)
2018/ 01/30Sparse disparity estimation for stereo matching acceleration (ICASSP 2018)
2018/ 01/11Proto-computing architecture over a digital medium aiming at real-time video processing (Complexity)
2017/ 12/27CNN accelerator design on dynamically reconfigurable hardware platform (SASIMI 2018)
2017/ 11/17BRein memory: a reconfigurable DNN accelerator chip (IEEE JSSC)
2017/ 11/15QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS (ISSCC 2018)
2017/ 09/08Quantization Error-based Regularization in Neural Networks (SGAI 2017 & HENND2017)
2017/ 09/05Accelerating Deep Learning by Binarized Hardware (APSIPA ASC 2017)
2017/ 09/05Logarithmic Compression for Memory Footprint Reduction in Neural Network Training (CSA 2017)
2017/ 08/07Sign-invariant unsupervised learning for analog neural-network devices (JNNS & NOLTA 2017)
2017/ 08/04Won the best presentation award (IPSJ SIG-ARC)
2017/ 07/11Won the best presentation award (IEICE-RECONF)
2017/ 06/27Won the best presentation award (IEICE-CPSY)
2017/ 06/08Won the best presentation award (IPSJ SIG-ARC)
2017/ 05/29In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks (MWSCAS2017)
2017/ 05/29A Multithreaded CGRA for Convolutional Neural Network Processing (Circuits and Systems)
2017/ 05/06Poster presentations of image sensors and Ising machines (LSI and System Workshop 2017)
2017/ 05/01A Time-Division Multiplexing Ising Machine on FPGAs (HEART 2017)
2017/ 05/01Research presentations of deep learning and Ising machine (IEICE-RECONF/CPSY)
2017/ 05/01Accelerating ZDD Construction by Lazy Evaluation for Optimizing Memory Access Patterns (The 30th Workshop on Circuits and Systems)
2017/ 04/24A dynamic reconfigurable array accelerator for embedded microprocessor (Circuits and Systems)
2017/ 03/31A scalable ising model implementation on an FPGA (COOL Chips 20)
2017/ 03/28An energy-efficient dynamic branch predictor with naive Bayes classifier (NOLTA Journal)
2017/ 03/15Won the student paper award (NCSP 2017)
2017/ 03/14BRein memory: reconfigurable in-memory deep neural network accelerator (VLSI 2017 Symposia)
2017/ 01/12Research Trends of Hardware Deep Learning Accelerators (IEICE Synposium 2017)
2017/ 01/05Camera-position and posture estimation based on local patches of image sequences (NCSP 2017)
2016/ 10/18Technical presentations at IEICE ICD/CPSY Workshop for Young Researchers

Evolution of Application-Oriented Custom Architecture, Circuit, and Software Technology for Them

Shinya Takamaeda-Yamazaki

Associate Professor (LINDA), IST, Hokkaido University
Office: IST, M-BLDG, 2F, Room M203 (TEL: +81 11-706-6233, FAX: +81 11-706-7890)
E-mail: takamaeda at ist.hokudai.ac.jp

Research Topics

My research goal is to realize an efficient custom computer that employs reconfigurable devices, such as FPGA, and novel accelerator devices. I am working on the researches of application-specific accelerator hardware systems and system software, such as compiler and language, for easy and effective hardware development. (LINK to my personal page)

Academic Societies

  1. Institute of Electrical and Electronic Engineers (IEEE)
  2. The Institute of Electronics, Information and Communication Engineers (IEICE)
  3. Information Processing Society of Japan (IPSJ)

Lectures

  1. Digital Circuit Design (undergraduate school)
  2. Electrical and Electronic Engineering Laboratories (undergraduate school)
  3. System Applications of LSIs (graduate school)