Welcome to Laboratories for Advanced LSI Engineering (LALSIE)

Laboratories for Advanced LSI Engineering (LALSIE) represent an association of the following integrated circuits and systems research laboratories:

in Faculty of Information Science & Technology (IST), Hokkaido University, Japan.

Laboratory for Integrated Digital System Architecture (LINDA) handles advanced LSI architecture technologies in terms of software/hardware co-creation, aiming at sustainable development of efficient information-processing systems in the end of the Moore's law era.

Laboratory for Integrated NanoSystems (LINAS) challenges to invent integrated nano-systems exploiting innovative circuit/device co-design science and technologies. We develop device-aware circuits and information processing systems that utilize essential properties of emerging nano materials and devices, through interdisciplinary technologies and studies on semiconductor physics, integrated circuit engineering, information science, nonlinear theory and its applications, neural science, etc.

Latest News

2020/ 01/07Presentation at NCSP 2020 on hardware reservoir computing
2019/ 12/26Presentation at IEICE NLP on reservoir computing and ternary backpropergation
2019/ 12/01Associate Professor Megumi Akai-Kasaya joined Laboratory for Integrated NanoSystems (LINAS)
2019/ 10/20Won the Maker of Merit 2019! (Maker Faire Roma 2019)
2019/ 10/17FPGA2I won the NoMaps Prize in NoMaps NEDO Dream Pitch 2019
2019/ 10/07Exhibision of FPGA-AI (FPGA2I) Shield for Arduino at Maker Faire Rome 2019
2019/ 10/01FPGA accelerator for ternarized backpropagation (ReConFig 2019)
2019/ 09/20Bayesian neural networks accelerators (CANDAR 2019)
2019/ 07/11Dither NN: hardware/algorithm co-design for accurate quantized NN (IEICE Trans. D)
2019/ 06/27Lightweight BP algorithm for an edge-AI devices (NOLTA J.)
2019/ 06/21FPGA-based annealing processor (IEICE Trans. D)
2019/ 04/26Hardware-oriented algorithm and architecture for generative adversarial networks (JSP)
2019/ 04/01Prof. Motomura has been transferred to TITECH, Japan.
2019/ 03/26Won the Award from Dean of Graduate School of Information Science and Technology!
2019/ 03/26Won the Award from Dean of Engineering!
2019/ 03/07Won the NCSP'19 Student Paper Award!
2019/ 02/07Won the best presentation award! (IEICE RECONF)
2019/ 02/07Won the IPSJ Computer Science Research Award for Young Scientists!
2019/ 02/07Won the IEEE SSCS Predoctoral Achievement Award!
2019/ 02/07Our paper about log-quantized DNN LSI has been accepted by IEEE JSSC
2019/ 02/07Won the JSPS IKUSHI prize!
2019/ 01/20Ternarized backpropagation (RIEC International Symposium 2019)
2019/ 01/15GAN and reservoir computing (NCSP 2019)
2019/ 01/08Won the Best Paper Award! (JKCCS 2019)
2019/ 01/01Reservoir computing with Schmitt trigger networks (JKCCS 2019)
2018/ 12/13Won the Best Paper Award at FPT'18.
2018/ 09/16Dither NN: an accurate neural network with dithering for low bit-precision hardwarel (FPT'18)
2018/ 09/04Ternary back propagation algorithm for embedded egde-AI processing (JNNS 2018 Satellite WS)
2018/ 08/30Analysis of smoothed LHE methods for processing images with optical illusionsl (IEEE VCIP 2018)
2018/ 07/13A molecular neuromorphic network device (Nature Communications)
2018/ 06/28Log-quantized DNN Accelerator with shared accumulators (MCSoC 2018)
2018/ 06/27Hardware-aware neural networks and training methods (IEICE NOLTA Journal)
2018/ 05/15Won the IEEE SSCS Japan Chapter Academic Research Award at LSI and Systems Workshop 2018.
2018/ 05/15Won the IEICE ICD Student Poster Award at LSI and Systems Workshop 2018.
2018/ 05/05Deep learning model and its hardware (IEICE RECONF)
2018/ 05/05Won ISSCC 2018 Silk Road Award!
2018/ 04/09Presentation at IEICE NOLTA Society Meeting 2018
2018/ 03/26Won the SASIMI 2018 Young Researcher Award!
2018/ 02/13A novel iris-center detection algorithm towards gaze estimation (IWMA 2018)
2018/ 01/30Sparse disparity estimation for stereo matching acceleration (ICASSP 2018)
2018/ 01/11Proto-computing architecture over a digital medium aiming at real-time video processing (Complexity)
2017/ 12/27CNN accelerator design on dynamically reconfigurable hardware platform (SASIMI 2018)
2017/ 11/17BRein memory: a reconfigurable DNN accelerator chip (IEEE JSSC)
2017/ 11/14QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS (ISSCC 2018)
2017/ 10/19Intited talks on deep learning chips (SPI Forum 2017)
2017/ 09/08Quantization Error-based Regularization in Neural Networks (SGAI 2017 & HENND2017)
2017/ 09/05Accelerating Deep Learning by Binarized Hardware (APSIPA ASC 2017)
2017/ 09/05Logarithmic Compression for Memory Footprint Reduction in Neural Network Training (CSA 2017)
2017/ 08/07Sign-invariant unsupervised learning for analog neural-network devices (JNNS & NOLTA 2017)
2017/ 08/04Won the best presentation award (IPSJ SIG-ARC)
2017/ 07/10Won the best presentation award (IEICE-RECONF)
2017/ 06/27Won the best presentation award (IEICE-CPSY)
2017/ 06/08Won the best presentation award (IPSJ SIG-ARC)
2017/ 05/29In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks (MWSCAS2017)
2017/ 05/29A Multithreaded CGRA for Convolutional Neural Network Processing (Circuits and Systems)
2017/ 05/05Poster presentations of image sensors and Ising machines (LSI and System Workshop 2017)
2017/ 05/05Presentation at IEICE RECONF
2017/ 05/01Time-Division Multiplexing Ising Machine on FPGAs (HEART 2017)
2017/ 05/01Research presentations of deep learning and Ising machine (IEICE-RECONF/CPSY)
2017/ 05/01Accelerating ZDD Construction by Lazy Evaluation for Optimizing Memory Access Patterns (The 30th Workshop on Circuits and Systems)
2017/ 04/24A dynamic reconfigurable array accelerator for embedded microprocessor (Circuits and Systems)
2017/ 04/19LSIとシステムのワークショップ2017にてAIチップ動向に関する招待講演を行います。
2017/ 03/31A scalable ising model implementation on an FPGA (COOL Chips 20)
2017/ 03/28An energy-efficient dynamic branch predictor with naive Bayes classifier (NOLTA Journal)
2017/ 03/15Won the student paper award (NCSP 2017)
2017/ 03/14BRein memory: reconfigurable in-memory deep neural network accelerator (VLSI 2017 Symposia)
2017/ 02/18Live demonstration of feature extraction FPGA systems at ISCAS 2017
2017/ 02/09Deep learning chips and AI computing (JSAP Spring Symposium 2017)
2017/ 02/06Exploring optimized accelerator design for binarizedl CNN (IJCNN 2017)
2017/ 01/12Research Trends of Hardware Deep Learning Accelerators (IEICE Synposium 2017)
2017/ 01/05Camera-position and posture estimation based on local patches of image sequences (NCSP 2017)
2017/ 01/03Invited talk on deep learning and neuro chip at Kyushu University
2016/ 12/07Low latency divider using ensemble of moving average curves (ISQED 2017)
2016/ 10/19Invited talk: trends on deep learning and neuro chips (JEITA)
2016/ 10/18Technical presentations at IEICE ICD/CPSY Workshop for Young Researchers
2016/ 10/03Associate Professor Shinya Takamaeda joined Laboratory for Integrated Digital System Architecture (LINDA)
2016/ 09/29Dr. Hiroshi Momose joined Laboratory for Integrated NanoSystems (LINAS)
2016/ 09/22FPGA systems for super resolution and time-series forecasting (ReConFig 2016)
2016/ 09/05Won the best presentation award (IEICE Reconfigurable Systems Workshop)
2016/ 08/05Reconfigurable processor array architecture for DCNN (SASIMI 2016)
2016/ 07/23Naive Bayes classifier for dynamic branch prediction (APCCAS 2016)
2016/ 07/07A hardware cellular-automaton architecture for spatial pattern generation (NOLTA 2016)
2016/ 06/21Error tolerance analysis of deep learning hardware towards low-power memory implementation (IEEE TCAS2)
2016/ 06/13A novel iris-center detection architecture towards gaze estimation (IEICE Symposium)
2016/ 06/08Image sensor/processor 3D stacked system featuring ThruChip interfaces (ESSCIRC 2016)
2016/ 05/09Reliability of error-injected hardware DBN (NOLTA Journal)
2016/ 05/06FPGA-based stream processing for frequent itemset mining (J. Circuits and Systems)
2016/ 04/21FPGA implementation of restricted Boltzmann machines (J. Circuits and Systems)
2016/ 04/053D stacked imager featuring ThruChip Interfaces (ITE Trans. MTA)
2016/ 04/01New LALSIE, an association of Laboratory for Integrated Digital System Architecture (LINDA) and for Integrated NanoSystems (LINAS) has been lauched.
2016/ 04/01Professor Tetsuya Asai joined Laboratory for Integrated NanoSystems (LINAS)
2016/ 03/31Hardware-Oriented Celullar Automata for Gaze Estimation (IEICE NOLTA Society Symposium)
2016/ 03/31Hardware Architecture for Online Frequent Items Mining (COOL Chips XIX)
2016/ 03/31Presentations at IEICE LSI and Systems Workshop 2016
2016/ 03/11Stream Processing Architectures for Frequent Itemset Mining (IEICE Reconfigurable Systems Workshop)
2016/ 03/10Deep Learning (CNN/RNN) Architectures (IEICE Reconfigurable Systems Workshop)
2016/ 01/13Memory-Error Tolerance of Hardware Deep Belief Networks (ISCAS 2016)
2015/ 12/22Call for Positions: Associate Professor in LALSIE (deadline: 22nd Apr, 2016)
2015/ 12/14Stochastic Resonance induced by Internal Noise (NOLTA Journal)
2015/ 12/05Whereabouts of Neuromorphic Engineering and Machine-learning Hardware (Invited Paper, JNNS)
2015/ 10/29Overview of Machine Learning Hardware (Invited, NICT-CiNet Seminar)
2015/ 09/10Accelerating Intelligent Information Processing by Hardware (Invited Talk at STARC Forum 2015)
2015/ 09/01Nonlinear Image Processing Algorithms (NICT-CiNet Seminar)
2015/ 08/16Overview of Neuromorphic Systems / Chips (STARC Advanced Seminar; Neuro Chip 1)
2015/ 08/01Nonlinear / Noise-driven Information Processing (NOLTA 2015)
2015/ 04/07Neural Networks on FPGA (Invited Talk at JNNS Symposium 2015)
2015/ 04/02Won the Best Paper Award! (Research Institute of Signal Processing Japan)
2015/ 03/31Digitral Machine Learning Systems (Invited Talk at Brainware Engineering Workshop)
2015/ 03/11Image sensor/digital logic 3D stacked module (2015 VLSI Symposia)
2015/ 03/05TCI crosstalk rejection based on blind source separation (IEEE TCAS-II)
2015/ 01/13A scalable FPGA-based architecture for locality-sensitive hashing (IEICE Conference)
2015/ 01/05Nonlinear Signal-Processing Gadgets (NCSP 2015)
2014/ 12/29An accelerator for frequent Itemset mining from data stream (SASIMI 2015)
2014/ 12/25FPGA implementation of hardware-oriented RDCA (NOLTA Journal)
2014/ 12/09Caching memcached at reconfigurable network interface (IPSJ Journal)
2014/ 10/28Won the Best Student Paper Award at JKCCS 2014
2014/ 10/15Presentation at IEICE ICD/CPSY Workshop
2014/ 10/02Achieving higher performance of memcached by caching at network interface (ICFPT 2014)
2014/ 09/06Hardware architecture for accelerating key-value retrieval implemented on FPGA (JKCCS 2014)
2014/ 09/03Low-power NV microcontrollers with transparent on-chip instruction cache (CS Journal)
2014/ 08/31Transparent on-chip instruction cache for NV microcontrollers (CENICS 2014)
2014/ 08/20Mainly-static/partially-dynamic reconfigurable array accelerator (A-SSCC 2014)
2014/ 07/15Self-driven Stochastic Resonance (IEICE NetSci/CCS workshop 2014).
2014/ 07/10Low-power asynchronous digital pipeline based on stochastic ogic gates (ELEX)
2014/ 06/18Hardware-Oriented Reaction-Diffusion Steganography (NOLTA Journal)
2014/ 06/18Low-Power Logic Gates utilizing Stochastic Resonance (NOLTA Journal)
2014/ 06/09Won the Student Presentation Award of 2013 IEICE CS Workshop!
2014/ 06/06Stochastic Resonance Applications (NOLTA 2014, Special Session)
2014/ 06/04Caching memcached at reconfigurable network interface (FPL 2014)
2014/ 05/09Morphic Architectures for Molecular Architectonics (MOLARCH WS)
2014/ 05/01Machine Learning of Motion Vectors exploiting High-Speed Imaging (JSP)
2014/ 04/08Presentation at LSI and Systems Workshop 2014
2014/ 03/03Won the student paper award (NCSP 2014)
2014/ 02/21Stochastic Circuit Design for Molecular Architectonics (MolArch Workshop 2014)
2014/ 01/08Dynamic Load Generator for Memcached Evaluation (IEICE)
2014/ 01/07FPGA implementation of a novel stereo vision algorithm (CSC 2014)
2014/ 01/06Machine Learning of Motion Vectors exploiting High-Speed Imaging (NCSP 2014)
2013/ 12/17Low-power flash-based microcontrollers architecture (ARC workshop)
2013/ 12/11Stereo Matching VLSI Architectures (STARC Symposium 2014)
2013/ 11/20FPGA Implementation of Cached NIC for Memcashed (IEICE RECONF Workshop)
2013/ 11/19Machine learning of motion vectors on FPGA (IEICE ICD Workshop)
2013/ 11/18Won the best student paper award of NOLTA 2013!
2013/ 11/13Journal Paper: C-based design for dynamically reconfigurable hardware
2013/ 10/18FPGA Implementation of Reaction-Diffusion Cellular Automata (SRBA 2013)
2013/ 10/15Hardware-oriented stereo vision algorithm and its FPGA implementation (ICECS 2013)
2013/ 09/27A restricted dynamically reconfigurable architecture (ReConFig 2013)
2013/ 09/27Image steganography based on RD models and its FPGA implementation (SICE SSI 2013)
2013/ 09/07Low power reconf and stream processors (IEICE Reconf WS)
2013/ 08/08Presentation: Depth map FPGA (VDEC Designer's Forum)
2013/ 08/06Presentation: dynamically reconfigurable technologies (SASIMI 2013)
2013/ 07/22Journal Paper: chaotic Resonance (J. Signal Processing)
2013/ 07/12Presentation: logical stohastic resonance (IEICE NetSci/CCS workshop, 2013)
2013/ 05/27Presentation: image steganography processor (NDES 2013)
2013/ 05/16Presentation: reaction diffusion steganography (IEICE CCS WS, 2013)
2013/ 05/16Presentation: applications of nonlinear systems (NOLTA 2013)
2013/ 05/15Award: student poster award at LSI and Systems Workshop 2013!
2013/ 04/23Presentation: asynchronous digital circuits based on stochastic resonance (NANOENERGY 2013)
2013/ 04/22Jounal Paper: single-image super resolution on FPGA (J. Signal Processing)
2013/ 04/17Presentation: C-based design for dynamially reconfigurable hardware (IEICE IN 2013)
2013/ 04/17Presentation: implementing window-join on DRP HPCS 2013
2013/ 03/27Presentation: restricted dynamically reconficurable processor (SACSIS 2013)
2013/ 03/11Award: Student Paper Award (NSCP'13)
2013/ 01/03Presentation: sensor-processor 3D integration (STARC Symposium 2013)
2013/ 01/03Presentation: FPGA implementation of single-image super resolution (NCSP 2013)
2012/ 12/11Presentation: Stream processing on dynamically reconfigurable hardware (ARC 2013)
2012/ 12/04Presentation: Array-enhanced chaoric resonance (IEICE NLP, Jan. 2013)
2012/ 11/26Keynote talk: IEICE VLD - Design Gaia 2012 (Prof. Motomura)
2012/ 09/24Journal Paper: Noise-driven active transmission line (J. Signal Processing)
2012/ 07/23Presentation: Nonlinear Analog Gadgets (AsiaNANO 2012)
2012/ 07/02Presentation: Reaction-diffusion media with memristors (CNNA 2012)
2012/ 06/18Presentation: Noise-induced spike transmission on electrical axon (NOLTA 2012)
2012/ 05/22Journal Paper: Nonlinear Electric Circuits (J. Signal Processing)
2012/ 05/02Presentation: low power processors (LSI and Systems Workshop 2012)
2012/ 04/02Presentation: Stochastic resonance in myelinated axons (ICCNS 2012)
2012/ 03/09Award: Student Paper Awards (NSCP'12)
2012/ 01/13Presentation: 2012 IEICE General Conference
2012/ 01/13Presentation: Nonlinear and neuromorphic electrical circuits (NCSP 2012)
2011/ 09/15Presentation: Noise-induced phase synchronization among analog MOS oscillator circuits (FNL)
2011/ 07/07Presentation: 2011 IEICE Society Conference (Sapporo, Japan)
2011/ 06/20Journal Paper: SR system consisting of single OTA (NOLTA Journal)
2011/ 06/10Presentation: IEICE NLP workshop (Hokkaido, 30th Jun, 2011)
2011/ 05/28Professor Motomura received the IEICE Achievement Award
2011/ 04/01Professor Masato Motomura joined with us, welcome!!